[llvm] 44c9e46 - [InstrRef] Fix mismatch between LiveDebugValues and salvageCopySSA (#124233)

[via llvm-commits]

Author: Shubham Sandeep Rastogi
Date: 2025-01-27T09:26:22-08:00
New Revision: 44c9e46fce12badae8cd3f5bd53fe1c2b1248940

URL: https://github.com/llvm/llvm-project/commit/44c9e46fce12badae8cd3f5bd53fe1c2b1248940
DIFF: https://github.com/llvm/llvm-project/commit/44c9e46fce12badae8cd3f5bd53fe1c2b1248940.diff

LOG: [InstrRef] Fix mismatch between LiveDebugValues and salvageCopySSA (#124233)

The LiveDebugValues pass and the instruction selector (which calls
salvageCopySSA) need to be consistent on what they consider a copy
instruction. With https://github.com/llvm/llvm-project/pull/75184, the
definition of what a copy instruction is was narrowed for AArch64 to
exclude a w->x ORR and treat it as a zero-extend rather than a copy

However, to make sure LiveDebugValues still treats a w->x ORR as a copy,
the new function, isCopyLikeInstr was created. We need to make sure that
salvageCopySSA also calls that function.

This patch addresses this mismatch.

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineFunction.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index ab3609b6141b8e..7d504ef5a0482e 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -1054,7 +1054,7 @@ auto MachineFunction::salvageCopySSA(
   // Check whether this copy-like instruction has already been salvaged into
   // an operand pair.
   Register Dest;
-  if (auto CopyDstSrc = TII.isCopyInstr(MI)) {
+  if (auto CopyDstSrc = TII.isCopyLikeInstr(MI)) {
     Dest = CopyDstSrc->Destination->getReg();
   } else {
     assert(MI.isSubregToReg());
@@ -1138,7 +1138,7 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
     CurInst = Inst.getIterator();
 
     // Any non-copy instruction is the defining instruction we're seeking.
-    if (!Inst.isCopyLike() && !TII.isCopyInstr(Inst))
+    if (!Inst.isCopyLike() && !TII.isCopyLikeInstr(Inst))
       break;
     State = GetRegAndSubreg(Inst);
   };