[llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

[Sam Tebbs via llvm-commits]

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@@ -5263,6 +5273,65 @@ SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
 
 static MVT getSVEContainerType(EVT ContentTy);
 
+SDValue AArch64TargetLowering::LowerALIAS_LANE_MASK(SDValue Op,
+                                                    SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  unsigned IntrinsicID = 0;
+  uint64_t EltSize = Op.getOperand(2)->getAsZExtVal();
+  bool IsWriteAfterRead = Op.getOperand(3)->getAsZExtVal() == 1;
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SamTebbs33 wrote:

Done.

https://github.com/llvm/llvm-project/pull/117007