[llvm] [GISel][AMDGPU] Fold ShuffleVec into ExtractSubvec, and custom lower ExtractSubvec (PR #124527)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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``````````bash
git-clang-format --diff 8035d38daab028b8da3cf2b01090b5f0ceacd695 89cccb419fdb5bc6da70d84da90efdbce040d64a --extensions cpp,h -- llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index fca7a81dd5..db89bd0532 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -384,12 +384,13 @@ void CombinerHelper::applyCombineConcatVectors(
   MI.eraseFromParent();
 }
 
-bool CombinerHelper::matchCombineShuffleExtract(MachineInstr &MI, int64_t &Idx) const {
+bool CombinerHelper::matchCombineShuffleExtract(MachineInstr &MI,
+                                                int64_t &Idx) const {
   assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
          "Invalid instruction");
   auto &Shuffle = cast<GShuffleVector>(MI);
   const auto &TLI = getTargetLowering();
-  
+
   auto SrcVec1 = Shuffle.getSrc1Reg();
   auto SrcVec2 = Shuffle.getSrc2Reg();
   auto Mask = Shuffle.getMask();
@@ -412,7 +413,8 @@ bool CombinerHelper::matchCombineShuffleExtract(MachineInstr &MI, int64_t &Idx)
   return true;
 }
 
-void CombinerHelper::applyCombineShuffleExtract(MachineInstr &MI, int64_t Idx) const {
+void CombinerHelper::applyCombineShuffleExtract(MachineInstr &MI,
+                                                int64_t Idx) const {
   auto &Shuffle = cast<GShuffleVector>(MI);
 
   auto SrcVec1 = Shuffle.getSrc1Reg();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 68b0a8b5ae..d902b06e6e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1834,9 +1834,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
   }
 
   getActionDefinitionsBuilder(G_EXTRACT_SUBVECTOR)
-    //.fewerElementsIf(isWideVec16(0), changeTo(0, V2S16))
-    .customFor({V8S16, V4S16})
-    .lower();
+      //.fewerElementsIf(isWideVec16(0), changeTo(0, V2S16))
+      .customFor({V8S16, V4S16})
+      .lower();
 
   getActionDefinitionsBuilder(G_EXTRACT_VECTOR_ELT)
     .unsupportedIf([=](const LegalityQuery &Query) {
@@ -2724,8 +2724,8 @@ bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(LegalizerHelper &Helper,
   return Helper.lowerFMinNumMaxNum(MI) == LegalizerHelper::Legalized;
 }
 
-static auto buildExtractSubvector(MachineIRBuilder &B, SrcOp Src,
-                                  LLT DstTy, unsigned Start) {
+static auto buildExtractSubvector(MachineIRBuilder &B, SrcOp Src, LLT DstTy,
+                                  unsigned Start) {
   SmallVector<Register, 8> Subvectors;
   for (unsigned i = Start, e = Start + DstTy.getNumElements(); i != e; ++i) {
     Subvectors.push_back(
@@ -2735,9 +2735,9 @@ static auto buildExtractSubvector(MachineIRBuilder &B, SrcOp Src,
   return B.buildBuildVector(DstTy, Subvectors);
 }
 
-bool AMDGPULegalizerInfo::legalizeExtractSubvector(
-  MachineInstr &MI, MachineRegisterInfo &MRI,
-  MachineIRBuilder &B) const {
+bool AMDGPULegalizerInfo::legalizeExtractSubvector(MachineInstr &MI,
+                                                   MachineRegisterInfo &MRI,
+                                                   MachineIRBuilder &B) const {
   const auto &Instr = llvm::cast<GExtractSubvector>(MI);
   Register Src = Instr.getSrcVec();
   Register Dst = MI.getOperand(0).getReg();

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https://github.com/llvm/llvm-project/pull/124527