[llvm] [WIP][RISCV] Support for zvzip fasttrack proposal (PR #124140)

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git-clang-format --diff 589593254eede2f624f29390dc1018725e536505 09265562a95dd37cb882a5bc875f2b5eae1d1f34 --extensions cpp,h -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6d812584ce..1cc0ce5a44 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4946,11 +4946,9 @@ static SDValue lowerZVZIP(unsigned Opc, SDValue Op0, SDValue Op1,
     // unzip2a and unzip2b must have an undef operand if < m1
     assert(RISCVISD::VUNZIP2A_VL != Opc || RISCVISD::VUNZIP2B_VL != Opc ||
            Op1.isUndef());
-    Op0 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, M1VT,
-                      DAG.getUNDEF(M1VT), Op0,
+    Op0 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, M1VT, DAG.getUNDEF(M1VT), Op0,
                       DAG.getVectorIdxConstant(0, DL));
-    Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, M1VT,
-                      DAG.getUNDEF(M1VT), Op1,
+    Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, M1VT, DAG.getUNDEF(M1VT), Op1,
                       DAG.getVectorIdxConstant(0, DL));
     InnerVT = M1VT;
   }
@@ -4968,11 +4966,10 @@ static SDValue lowerZVZIP(unsigned Opc, SDValue Op0, SDValue Op1,
 
   auto [Mask, VL] = getDefaultVLOps(IntVT, InnerVT, DL, DAG, Subtarget);
   SDValue Passthru = DAG.getUNDEF(InnerVT);
-  SDValue Res =
-    DAG.getNode(Opc, DL, InnerVT, Op0, Op1, Passthru, Mask, VL);
+  SDValue Res = DAG.getNode(Opc, DL, InnerVT, Op0, Op1, Passthru, Mask, VL);
   if (InnerVT.bitsGT(ContainerVT))
-    Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ContainerVT,
-                      Res, DAG.getVectorIdxConstant(0, DL));
+    Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ContainerVT, Res,
+                      DAG.getVectorIdxConstant(0, DL));
   else if (InnerVT.bitsLT(ContainerVT))
     Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT,
                       DAG.getUNDEF(ContainerVT), Res,
@@ -4983,7 +4980,6 @@ static SDValue lowerZVZIP(unsigned Opc, SDValue Op0, SDValue Op1,
   return Res;
 }
 
-
 // Given two input vectors of <[vscale x ]n x ty>, use vwaddu.vv and vwmaccu.vx
 // to create an interleaved vector of <[vscale x] n*2 x ty>.
 // This requires that the size of ty is less than the subtarget's maximum ELEN.
@@ -5658,7 +5654,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
     }
   }
 
-  if (Subtarget.hasStdExtZvzip())  {
+  if (Subtarget.hasStdExtZvzip()) {
     // If this is a deinterleave(2) - possibly with two distinct sources, and
     // possibly at e64 - match to the vunzip2a/vunzip2b.  Put this after the
     // vnsrl matching as that's probably still a better canonical form.
@@ -5674,8 +5670,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
       bool KnownLayout = false;
       if (auto VLEN = Subtarget.getRealVLen())
         KnownLayout = VT.getSizeInBits().getKnownMinValue() % *VLEN == 0;
-      unsigned Opc = Index == 0 ?
-          RISCVISD::VUNZIP2A_VL : RISCVISD::VUNZIP2B_VL;
+      unsigned Opc = Index == 0 ? RISCVISD::VUNZIP2A_VL : RISCVISD::VUNZIP2B_VL;
       if (V2.isUndef() || KnownLayout) {
         return lowerZVZIP(Opc, V1, V2, DL, DAG, Subtarget);
       } else if (NumElts < MinVLMAX) {
@@ -5746,13 +5741,12 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
     // Prefer vzip2a if available.
     // FIXME: prefer the spread idioms?  And figure out what the equivalent are
     // for the vzip2a cases to avoid undef issues?
-    if (Subtarget.hasStdExtZvzip())  {
+    if (Subtarget.hasStdExtZvzip()) {
       EvenV = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT),
                           EvenV, DAG.getVectorIdxConstant(0, DL));
-      OddV = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT),
-                          OddV, DAG.getVectorIdxConstant(0, DL));
+      OddV = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), OddV,
+                         DAG.getVectorIdxConstant(0, DL));
       return lowerZVZIP(RISCVISD::VZIP2A_VL, EvenV, OddV, DL, DAG, Subtarget);
-
     }
     assert(VT.getScalarSizeInBits() < Subtarget.getELen());
     return getWideningInterleave(EvenV, OddV, DL, DAG, Subtarget);

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https://github.com/llvm/llvm-project/pull/124140