[llvm] [RISCV] Select Zvkb VANDN for shorter constant loading sequences (PR #123345)
Piotr Fusik via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 21 21:46:58 PST 2025
https://github.com/pfusik updated https://github.com/llvm/llvm-project/pull/123345
>From cb251f3ddab7823761d2637898e8a786d4dba589 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Mon, 20 Jan 2025 17:16:54 +0100
Subject: [PATCH] [RISCV] Select Zvkb VANDN for shorter constant loading
sequences
This extends PR #120221 to vector instructions.
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 19 +++++++-
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 21 ++++++++
llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll | 54 +++++++++++----------
llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll | 17 +++----
4 files changed, 74 insertions(+), 37 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 36292e3d572cb2..9855028ead9e20 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3224,8 +3224,25 @@ bool RISCVDAGToDAGISel::selectInvLogicImm(SDValue N, SDValue &Val) {
// Abandon this transform if the constant is needed elsewhere.
for (const SDNode *U : N->users()) {
- if (!ISD::isBitwiseLogicOp(U->getOpcode()))
+ switch (U->getOpcode()) {
+ case ISD::AND:
+ case ISD::OR:
+ case ISD::XOR:
+ if (!(Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()))
+ return false;
+ break;
+ case RISCVISD::VMV_V_X_VL:
+ if (!Subtarget->hasStdExtZvkb())
+ return false;
+ if (!all_of(U->users(), [](const SDNode *V) {
+ return V->getOpcode() == ISD::AND ||
+ V->getOpcode() == RISCVISD::AND_VL;
+ }))
+ return false;
+ break;
+ default:
return false;
+ }
}
// For 64-bit constants, the instruction sequences get complex,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index c69d8885175219..430d75e5cec5b2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -624,6 +624,13 @@ foreach vti = AllIntegerVectors in {
vti.RegClass:$rs2,
vti.ScalarRegClass:$rs1,
vti.AVL, vti.Log2SEW, TA_MA)>;
+ def : Pat<(vti.Vector (and (riscv_splat_vector invLogicImm:$rs1),
+ vti.RegClass:$rs2)),
+ (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)
+ (vti.Vector (IMPLICIT_DEF)),
+ vti.RegClass:$rs2,
+ invLogicImm:$rs1,
+ vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
@@ -758,6 +765,20 @@ foreach vti = AllIntegerVectors in {
GPR:$vl,
vti.Log2SEW,
TAIL_AGNOSTIC)>;
+
+ def : Pat<(vti.Vector (riscv_and_vl (riscv_splat_vector invLogicImm:$rs1),
+ (vti.Vector vti.RegClass:$rs2),
+ (vti.Vector vti.RegClass:$passthru),
+ (vti.Mask V0),
+ VLOpFrag)),
+ (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX#"_MASK")
+ vti.RegClass:$passthru,
+ vti.RegClass:$rs2,
+ invLogicImm:$rs1,
+ (vti.Mask V0),
+ GPR:$vl,
+ vti.Log2SEW,
+ TAIL_AGNOSTIC)>;
}
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
index b42fff91b1c472..cf73dceaae3064 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
@@ -1945,10 +1945,9 @@ define <vscale x 1 x i16> @vandn_vx_imm16(<vscale x 1 x i16> %x) {
;
; CHECK-ZVKB-LABEL: vandn_vx_imm16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: lui a0, 8
-; CHECK-ZVKB-NEXT: addi a0, a0, -1
+; CHECK-ZVKB-NEXT: lui a0, 1048568
; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
+; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0
; CHECK-ZVKB-NEXT: ret
%a = and <vscale x 1 x i16> splat (i16 32767), %x
ret <vscale x 1 x i16> %a
@@ -1965,10 +1964,9 @@ define <vscale x 1 x i16> @vandn_vx_swapped_imm16(<vscale x 1 x i16> %x) {
;
; CHECK-ZVKB-LABEL: vandn_vx_swapped_imm16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: lui a0, 8
-; CHECK-ZVKB-NEXT: addi a0, a0, -1
+; CHECK-ZVKB-NEXT: lui a0, 1048568
; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
+; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0
; CHECK-ZVKB-NEXT: ret
%a = and <vscale x 1 x i16> %x, splat (i16 32767)
ret <vscale x 1 x i16> %a
@@ -2018,11 +2016,10 @@ define <vscale x 1 x i64> @vandn_vx_imm64(<vscale x 1 x i64> %x) {
;
; CHECK-ZVKB64-LABEL: vandn_vx_imm64:
; CHECK-ZVKB64: # %bb.0:
-; CHECK-ZVKB64-NEXT: li a0, -1
-; CHECK-ZVKB64-NEXT: slli a0, a0, 56
-; CHECK-ZVKB64-NEXT: addi a0, a0, 255
+; CHECK-ZVKB64-NEXT: lui a0, 1048560
+; CHECK-ZVKB64-NEXT: srli a0, a0, 8
; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; CHECK-ZVKB64-NEXT: vand.vx v8, v8, a0
+; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a0
; CHECK-ZVKB64-NEXT: ret
%a = and <vscale x 1 x i64> %x, splat (i64 -72057594037927681)
ret <vscale x 1 x i64> %a
@@ -2041,11 +2038,10 @@ define <vscale x 1 x i16> @vandn_vx_multi_imm16(<vscale x 1 x i16> %x, <vscale x
;
; CHECK-ZVKB-LABEL: vandn_vx_multi_imm16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: lui a0, 4
-; CHECK-ZVKB-NEXT: addi a0, a0, -1
+; CHECK-ZVKB-NEXT: lui a0, 1048572
; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-ZVKB-NEXT: vand.vx v8, v8, a0
-; CHECK-ZVKB-NEXT: vand.vx v9, v9, a0
+; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0
+; CHECK-ZVKB-NEXT: vandn.vx v9, v9, a0
; CHECK-ZVKB-NEXT: vadd.vv v8, v8, v9
; CHECK-ZVKB-NEXT: ret
%a = and <vscale x 1 x i16> %x, splat (i16 16383)
@@ -2065,15 +2061,24 @@ define <vscale x 1 x i16> @vandn_vx_multi_scalar_imm16(<vscale x 1 x i16> %x, i1
; CHECK-NEXT: vadd.vx v8, v8, a0
; CHECK-NEXT: ret
;
-; CHECK-ZVKB-LABEL: vandn_vx_multi_scalar_imm16:
-; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: lui a1, 8
-; CHECK-ZVKB-NEXT: addi a1, a1, -1
-; CHECK-ZVKB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
-; CHECK-ZVKB-NEXT: vand.vx v8, v8, a1
-; CHECK-ZVKB-NEXT: or a0, a0, a1
-; CHECK-ZVKB-NEXT: vadd.vx v8, v8, a0
-; CHECK-ZVKB-NEXT: ret
+; CHECK-ZVKB-NOZBB-LABEL: vandn_vx_multi_scalar_imm16:
+; CHECK-ZVKB-NOZBB: # %bb.0:
+; CHECK-ZVKB-NOZBB-NEXT: lui a1, 8
+; CHECK-ZVKB-NOZBB-NEXT: addi a1, a1, -1
+; CHECK-ZVKB-NOZBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
+; CHECK-ZVKB-NOZBB-NEXT: vand.vx v8, v8, a1
+; CHECK-ZVKB-NOZBB-NEXT: or a0, a0, a1
+; CHECK-ZVKB-NOZBB-NEXT: vadd.vx v8, v8, a0
+; CHECK-ZVKB-NOZBB-NEXT: ret
+;
+; CHECK-ZVKB-ZBB-LABEL: vandn_vx_multi_scalar_imm16:
+; CHECK-ZVKB-ZBB: # %bb.0:
+; CHECK-ZVKB-ZBB-NEXT: lui a1, 1048568
+; CHECK-ZVKB-ZBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
+; CHECK-ZVKB-ZBB-NEXT: vandn.vx v8, v8, a1
+; CHECK-ZVKB-ZBB-NEXT: orn a0, a0, a1
+; CHECK-ZVKB-ZBB-NEXT: vadd.vx v8, v8, a0
+; CHECK-ZVKB-ZBB-NEXT: ret
%a = and <vscale x 1 x i16> %x, splat (i16 32767)
%b = or i16 %y, 32767
%head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
@@ -2104,6 +2109,3 @@ define <vscale x 1 x i16> @vand_vadd_vx_imm16(<vscale x 1 x i16> %x) {
%b = add <vscale x 1 x i16> %a, splat (i16 32767)
ret <vscale x 1 x i16> %b
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-ZVKB-NOZBB: {{.*}}
-; CHECK-ZVKB-ZBB: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
index 2a3069a97fd9fb..5d29b266546f59 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
@@ -1441,10 +1441,9 @@ define <vscale x 1 x i16> @vandn_vx_vp_imm16(<vscale x 1 x i16> %x, <vscale x 1
;
; CHECK-ZVKB-LABEL: vandn_vx_vp_imm16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: lui a1, 8
-; CHECK-ZVKB-NEXT: addi a1, a1, -1
+; CHECK-ZVKB-NEXT: lui a1, 1048568
; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-ZVKB-NEXT: vand.vx v8, v8, a1, v0.t
+; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a1, v0.t
; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 1 x i16> @llvm.vp.and.nxv1i16(<vscale x 1 x i16> splat (i16 32767), <vscale x 1 x i16> %x, <vscale x 1 x i1> %mask, i32 %evl)
ret <vscale x 1 x i16> %a
@@ -1461,10 +1460,9 @@ define <vscale x 1 x i16> @vandn_vx_vp_swapped_imm16(<vscale x 1 x i16> %x, <vsc
;
; CHECK-ZVKB-LABEL: vandn_vx_vp_swapped_imm16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: lui a1, 8
-; CHECK-ZVKB-NEXT: addi a1, a1, -1
+; CHECK-ZVKB-NEXT: lui a1, 1048568
; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-ZVKB-NEXT: vand.vx v8, v8, a1, v0.t
+; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a1, v0.t
; CHECK-ZVKB-NEXT: ret
%a = call <vscale x 1 x i16> @llvm.vp.and.nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i16> splat (i16 32767), <vscale x 1 x i1> %mask, i32 %evl)
ret <vscale x 1 x i16> %a
@@ -1514,11 +1512,10 @@ define <vscale x 1 x i64> @vandn_vx_vp_imm64(<vscale x 1 x i64> %x, <vscale x 1
;
; CHECK-ZVKB64-LABEL: vandn_vx_vp_imm64:
; CHECK-ZVKB64: # %bb.0:
-; CHECK-ZVKB64-NEXT: li a1, -1
-; CHECK-ZVKB64-NEXT: slli a1, a1, 56
-; CHECK-ZVKB64-NEXT: addi a1, a1, 255
+; CHECK-ZVKB64-NEXT: lui a1, 1048560
+; CHECK-ZVKB64-NEXT: srli a1, a1, 8
; CHECK-ZVKB64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-ZVKB64-NEXT: vand.vx v8, v8, a1, v0.t
+; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a1, v0.t
; CHECK-ZVKB64-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.vp.and.nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i64> splat (i64 -72057594037927681), <vscale x 1 x i1> %mask, i32 %evl)
ret <vscale x 1 x i64> %a
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