[llvm] [RISCV] Select Zvkb VANDN for shorter constant loading sequences (PR #123345)

[Piotr Fusik via llvm-commits]

================
@@ -3224,8 +3224,25 @@ bool RISCVDAGToDAGISel::selectInvLogicImm(SDValue N, SDValue &Val) {
 
   // Abandon this transform if the constant is needed elsewhere.
   for (const SDNode *U : N->users()) {
-    if (!ISD::isBitwiseLogicOp(U->getOpcode()))
+    switch (U->getOpcode()) {
+    case ISD::AND:
+    case ISD::OR:
+    case ISD::XOR:
+      if (!(Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()))
+        return false;
+      break;
+    case RISCVISD::VMV_V_X_VL:
+      if (!Subtarget->hasStdExtZvkb())
+        return false;
+      if (!all_of(U->users(), [](const SDNode *V) {
+            return V->getOpcode() == ISD::AND ||
+                   V->getOpcode() == RISCVISD::AND_VL;
----------------
pfusik wrote:

How to test? Is `@llvm.riscv.vand`'s first operand the passthru?

Would it be possible for the same `VMV_V_X_VL` to be the AND_VL passthru and one of the AND_VL "and" operands at the same time?

Would the following work:

```cpp
      if (!all_of(U->users(), [U](const SDNode *V) {
             return V->getOpcode() == ISD::AND ||
                   (V->getOpcode() == RISCVISD::AND_VL &&
                    U != V->getOperand(2).getNode()); // not passthru
           }))
```

?

https://github.com/llvm/llvm-project/pull/123345