[llvm] [RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (PR #123865)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

We had two WriteRes for WriteJalr with difference latencies. I don't know which is correct. I chose Latency=2 to match WriteJal.

---
Full diff: https://github.com/llvm/llvm-project/pull/123865.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td (-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
index 550f83a59b8b0e..ab6402dc96af10 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
@@ -125,7 +125,6 @@ def : WriteRes<WriteCSR, [p8700ALQ]>;
 
 // Handle CTI Pipeline.
 def : WriteRes<WriteJmp, [p8700IssueCTI]>;
-def : WriteRes<WriteJalr, [p8700IssueCTI]>;
 let Latency = 2 in {
 def : WriteRes<WriteJal, [p8700IssueCTI]>;
 def : WriteRes<WriteJalr, [p8700IssueCTI]>;

``````````

</details>


https://github.com/llvm/llvm-project/pull/123865