[llvm] [RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (PR #123865)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/123865

We had two WriteRes for WriteJalr with difference latencies. I don't know which is correct. I chose Latency=2 to match WriteJal.

>From 1e61a62cbf4b8800fbb6edef7c9a3e2744482a38 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 21 Jan 2025 17:42:48 -0800
Subject: [PATCH] [RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700.

We had two WriteRes for WriteJalr with difference latencies. I don't
know which is correct. I chose Latency=2 to match WriteJal.
---
 llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 -
 1 file changed, 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
index 550f83a59b8b0e..ab6402dc96af10 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
@@ -125,7 +125,6 @@ def : WriteRes<WriteCSR, [p8700ALQ]>;
 
 // Handle CTI Pipeline.
 def : WriteRes<WriteJmp, [p8700IssueCTI]>;
-def : WriteRes<WriteJalr, [p8700IssueCTI]>;
 let Latency = 2 in {
 def : WriteRes<WriteJal, [p8700IssueCTI]>;
 def : WriteRes<WriteJalr, [p8700IssueCTI]>;