[llvm] [llvm][Docs] Release note for LLDB optionally disabled regsets for RV64 (PR #123363)

[David Spickett via llvm-commits]

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@@ -483,6 +483,8 @@ Changes to LLDB
   to be opened in the firewall (one for the `lldb-server` platform, one for gdbserver connections).
   In addition, due to this work, `lldb-server` now works on Windows in the server mode.
 
+* LLDB now supports optionally enabled/disabled register sets (particularly FPR) for RISC-V 64. The situation might take place for RISC-V builds having no FP-registers, like RV64IMAC or RV64IMACV. The change is applied to native debugging or core-file usage. EmulateInstruction is out of scope of the change, so its behavior remains the same using the maximum set of registers.
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DavidSpickett wrote:

Write out the acronym, since we have the space to do that:
"(particularly floating point registers)"

I would be more certain here:
"This happens for targets like `RV64IMAC` or `RV64IMACV`, that have no floating point registers."

"native debugging and core-file usage" - just because the change was applied to both, there's no "or" here except for what the user chooses but that's up to them, not due to this change.

Users don't know what `EmulateInstruction` is, so perhaps you could say something like:
"Situations that require instruction emulation did not change, these still assume that all possible registers are present."

Which maybe I wouldn't have included at all, given that for unwinding and software single step, we hope the binary will not include instructions that interact with registers that don't exist.

Then again, maybe someone tries to debug floating point code on RV64IMAC without realising it and we happily single step through FP routines :)

(there's enough emulation in there to make a small simulator as it is)



https://github.com/llvm/llvm-project/pull/123363