[llvm] [AMDGPU] Reject misaligned SGPR constraints for inline asm (PR #123590)

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git-clang-format --diff 754ed95b6672b9a678a994cc652862a91cdc4406 19512cbd27bd7fbd58e6700128f95d40cc8b698c --extensions cpp -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 553ca9bb28..41a24a7793 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -15877,7 +15877,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
             RC = TRI->getAGPRClassForBitWidth(Width);
           if (RC) {
             Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0, RC);
-            if (!Reg ) {
+            if (!Reg) {
               // The register class does not contain the requested register,
               // e.g., because it is an SGPR pair that would violate alignment
               // requirements.

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https://github.com/llvm/llvm-project/pull/123590