[llvm] 4a486e7 - [CodeGen] Use Register/MCRegister::isPhysical. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 18 23:39:51 PST 2025
Author: Craig Topper
Date: 2025-01-18T23:37:03-08:00
New Revision: 4a486e773e0ef1add4515ee47b038c274ced2e76
URL: https://github.com/llvm/llvm-project/commit/4a486e773e0ef1add4515ee47b038c274ced2e76
DIFF: https://github.com/llvm/llvm-project/commit/4a486e773e0ef1add4515ee47b038c274ced2e76.diff
LOG: [CodeGen] Use Register/MCRegister::isPhysical. NFC
Added:
Modified:
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/MachineOperand.cpp
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/CodeGen/MachineRegisterInfo.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/TargetRegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
llvm/lib/Target/X86/X86RegisterInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index b95516f616e0f1..caec0524e7ab62 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -895,7 +895,7 @@ bool EarlyIfConverter::shouldConvertIf() {
if (!MO.isReg() || !MO.isUse())
return false;
Register Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
return false;
MachineInstr *Def = MRI->getVRegDef(Reg);
@@ -906,7 +906,7 @@ bool EarlyIfConverter::shouldConvertIf() {
if (!MO.isReg() || !MO.isUse())
return false;
Register Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
return false;
MachineInstr *Def = MRI->getVRegDef(Reg);
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 5ac6472a01e9fc..9bc8989cbfa1f6 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -644,7 +644,7 @@ void MachineBasicBlock::sortUniqueLiveIns() {
Register
MachineBasicBlock::addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC) {
assert(getParent() && "MBB must be inserted in function");
- assert(Register::isPhysicalRegister(PhysReg) && "Expected physreg");
+ assert(PhysReg.isPhysical() && "Expected physreg");
assert(RC && "Register class is required");
assert((isEHPad() || this == &getParent()->front()) &&
"Only the entry block and landing pads can have physreg live ins");
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 5c9ca91e784e9c..d11ac614ace356 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -91,7 +91,7 @@ void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
}
void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
- assert(Register::isPhysicalRegister(Reg));
+ assert(Reg.isPhysical());
if (getSubReg()) {
Reg = TRI.getSubReg(Reg, getSubReg());
// Note that getSubReg() may return 0 if the sub-register doesn't exist.
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index acd42aa497c6fe..54d9c1cf08e35b 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -3204,7 +3204,7 @@ bool SMSchedule::isValidSchedule(SwingSchedulerDAG *SSD) {
for (auto &OE : SSD->getDDG()->getOutEdges(&SU)) {
SUnit *Dst = OE.getDst();
if (OE.isAssignedRegDep() && !Dst->isBoundaryNode())
- if (Register::isPhysicalRegister(OE.getReg())) {
+ if (OE.getReg().isPhysical()) {
if (stageScheduled(Dst) != StageDef)
return false;
if (InstrToCycle[Dst] <= CycleDef)
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index 394b99b85ddcc5..532e537c2549cf 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -526,7 +526,7 @@ void MachineRegisterInfo::freezeReservedRegs() {
}
bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
- assert(Register::isPhysicalRegister(PhysReg));
+ assert(PhysReg.isPhysical());
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
if (TRI->isConstantPhysReg(PhysReg))
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index f8d7c3ef7bbe71..72557937a99bcb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -12769,7 +12769,7 @@ void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) {
// the OpInfo.ConstraintVT is legal on the target or not.
for (Register &Reg : OpInfo.AssignedRegs.Regs) {
Register OriginalDef = FollowCopyChain(MRI, InitialDef++);
- if (Register::isPhysicalRegister(OriginalDef))
+ if (OriginalDef.isPhysical())
FuncInfo.MBB->addLiveIn(OriginalDef);
// Update the assigned registers to use the original defs.
Reg = OriginalDef;
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 3be47a769d41d2..ba528f66980fa1 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -206,8 +206,7 @@ static const TargetRegisterClass *
getMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg,
TypeT Ty) {
static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);
- assert(Register::isPhysicalRegister(Reg) &&
- "reg must be a physical register");
+ assert(Reg.isPhysical() && "reg must be a physical register");
bool IsDefault = [&]() {
if constexpr (std::is_same_v<TypeT, MVT>)
@@ -235,8 +234,7 @@ static const TargetRegisterClass *
getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1,
MCRegister Reg2, TypeT Ty) {
static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);
- assert(Register::isPhysicalRegister(Reg1) &&
- Register::isPhysicalRegister(Reg2) &&
+ assert(Reg1.isPhysical() && Reg2.isPhysical() &&
"Reg1/Reg2 must be a physical register");
bool IsDefault = [&]() {
@@ -504,14 +502,13 @@ bool TargetRegisterInfo::getRegAllocationHints(
bool TargetRegisterInfo::isCalleeSavedPhysReg(
MCRegister PhysReg, const MachineFunction &MF) const {
- if (PhysReg == 0)
+ if (!PhysReg)
return false;
const uint32_t *callerPreservedRegs =
getCallPreservedMask(MF, MF.getFunction().getCallingConv());
if (callerPreservedRegs) {
- assert(Register::isPhysicalRegister(PhysReg) &&
- "Expected physical register");
- return (callerPreservedRegs[PhysReg / 32] >> PhysReg % 32) & 1;
+ assert(PhysReg.isPhysical() && "Expected physical register");
+ return (callerPreservedRegs[PhysReg.id() / 32] >> PhysReg.id() % 32) & 1;
}
return false;
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index a2fd4963db108e..6b8a7e9559e005 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -4830,7 +4830,7 @@ static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
if (!SubIdx)
return MIB.addReg(Reg, State);
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
return MIB.addReg(Reg, State, SubIdx);
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 9836e10c36bc5d..e9e47eaadd557f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -4280,7 +4280,7 @@ bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
const TargetRegisterClass *ArgRC,
LLT ArgTy) const {
MCRegister SrcReg = Arg->getRegister();
- assert(Register::isPhysicalRegister(SrcReg) && "Physical register expected");
+ assert(SrcReg.isPhysical() && "Physical register expected");
assert(DstReg.isVirtual() && "Virtual register expected");
Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg,
diff --git a/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
index 91c565ea00fbc2..d1b136429d3a4c 100644
--- a/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
@@ -171,7 +171,7 @@ void NVPTXRegisterInfo::addToDebugRegisterMap(
}
int64_t NVPTXRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
- if (Register::isPhysicalRegister(RegNum)) {
+ if (RegNum.isPhysical()) {
std::string name = NVPTXInstPrinter::getRegisterName(RegNum.id());
// In NVPTXFrameLowering.cpp, we do arrange for %Depot to be accessible from
// %SP. Using the %Depot register doesn't provide any debug info in
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 019d4cfa33fbaf..b60a91be824069 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -531,7 +531,7 @@ bool PPCRegisterInfo::requiresVirtualBaseRegisters(
bool PPCRegisterInfo::isCallerPreservedPhysReg(MCRegister PhysReg,
const MachineFunction &MF) const {
- assert(Register::isPhysicalRegister(PhysReg));
+ assert(PhysReg.isPhysical());
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
const MachineFrameInfo &MFI = MF.getFrameInfo();
diff --git a/llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp b/llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
index bf9b8e57305939..89a2146227bdd4 100644
--- a/llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
+++ b/llvm/lib/Target/X86/X86ArgumentStackSlotRebase.cpp
@@ -128,7 +128,7 @@ bool X86ArgumentStackSlotPass::runOnMachineFunction(MachineFunction &MF) {
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
- if (!Register::isPhysicalRegister(Reg))
+ if (!Reg.isPhysical())
continue;
if (TRI->isSuperOrSubRegisterEq(BasePtr, Reg))
return true;
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 164d4205955166..4faf8bca4f9e02 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -1183,8 +1183,7 @@ bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
auto TryAddNDDHint = [&](const MachineOperand &MO) {
Register Reg = MO.getReg();
- Register PhysReg =
- Register::isPhysicalRegister(Reg) ? Reg : Register(VRM->getPhys(Reg));
+ Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
if (PhysReg && !MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
TwoAddrHints.insert(PhysReg);
};
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