[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Sander de Smalen via llvm-commits]

================
@@ -1451,6 +1451,13 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // Nodes used to represent a partial reduction addition operation (signed and
+  // unsigned).
+  // Operands: Accumulator, Input
+  // Outputs: Output
----------------
sdesmalen-arm wrote:

Can you be more explicit about what the operation does and where the sign/zero-extension comes in?
Specifically, which operands are being multiplied (the comment describes only a single `Input`, I guess that's missing a second operand?)

As an example of what I mean, is this a valid use of `PARTIAL_REDUCE_SMLA`:
```
  nxv2i32 PARTIAL_REDUCE_SMLA(nxv2i32 %acc, nxv4i16 %a, nxv4i16 %b)
```
or should the `%acc` and the result have the same number of elements? And should they have the same element bitwidth? Should %a and %b have the same type?


https://github.com/llvm/llvm-project/pull/117185