[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Sander de Smalen via llvm-commits]

================
@@ -8135,15 +8135,19 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
     return;
   }
   case Intrinsic::experimental_vector_partial_reduce_add: {
+    SDLoc dl = getCurSDLoc();
+    SDValue Acc = getValue(I.getOperand(0));
+    EVT AccVT = Acc.getValueType();
+    SDValue Input = getValue(I.getOperand(1));
 
     if (!TLI.shouldExpandPartialReductionIntrinsic(cast<IntrinsicInst>(&I))) {
-      visitTargetIntrinsic(I, Intrinsic);
+      setValue(&I, DAG.getNode(ISD::PARTIAL_REDUCE_UMLA, dl, AccVT, Acc, Input,
+                               DAG.getConstant(1, dl, Input.getValueType())));
       return;
     }
-
-    setValue(&I, DAG.getPartialReduceAdd(sdl, EVT::getEVT(I.getType()),
-                                         getValue(I.getOperand(0)),
-                                         getValue(I.getOperand(1))));
+    setValue(&I,
+             DAG.expandPartialReduceAdd(
----------------
sdesmalen-arm wrote:

Did you consider always expanding the intrinsic to a PARTIAL_REDUCE_UMLA/SMLA ISD node, and only expand the operation in LegalizeVectorOps.cpp when there is no custom-lowering for it?

That avoids the need for calling `DAG.expandPartialReduceAdd` in `tryCombineToDotProduct`.

https://github.com/llvm/llvm-project/pull/117185