[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

[Shenglin Tang via llvm-commits]

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@@ -553,6 +553,37 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,
+                                          !listconcat(!listremove(RVA23S64Features,
+                                                      [FeatureStdExtZiccamoa,
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tangshenglin wrote:

V2R2 is a validated and stable release. Full support for RVA23 is also in the pipeline, with updates expected to be completed by 2025. The timeline will be dynamically adjusted based on progress. Once finalized, the XSCC team will synchronize updates accordingly.

https://github.com/llvm/llvm-project/pull/123193