[llvm] Add to/from SR instr usage and SR uses/defs (PR #122605)

via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 15 16:47:36 PST 2025


https://github.com/knickish updated https://github.com/llvm/llvm-project/pull/122605

>From 221f07cbd954167460476f9b66a95a2db2011582 Mon Sep 17 00:00:00 2001
From: kirk <knickish at gmail.com>
Date: Sat, 11 Jan 2025 12:33:09 -0600
Subject: [PATCH] Add to/from SR instr usage and SR uses/defs

---
 llvm/lib/Target/M68k/M68kInstrArithmetic.td   | 24 +++++++-------
 llvm/lib/Target/M68k/M68kInstrBits.td         |  4 +--
 llvm/lib/Target/M68k/M68kInstrCompiler.td     |  4 +--
 llvm/lib/Target/M68k/M68kInstrData.td         | 32 +++++++++++--------
 llvm/lib/Target/M68k/M68kInstrInfo.cpp        |  3 ++
 llvm/lib/Target/M68k/M68kInstrInfo.td         |  4 +++
 llvm/lib/Target/M68k/M68kInstrShiftRotate.td  |  4 +--
 llvm/lib/Target/M68k/M68kRegisterInfo.td      |  2 +-
 llvm/lib/Target/M68k/M68kSubtarget.h          |  7 ++++
 llvm/test/CodeGen/M68k/CConv/rtd-call.ll      | 12 +++----
 .../M68k/is-pcrel-register-operand-legal.mir  |  4 +--
 11 files changed, 59 insertions(+), 41 deletions(-)

diff --git a/llvm/lib/Target/M68k/M68kInstrArithmetic.td b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
index e2d4e49ddf27b6..c74ed2cf07216d 100644
--- a/llvm/lib/Target/M68k/M68kInstrArithmetic.td
+++ b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
@@ -53,7 +53,7 @@ def MxOpMode32_a_EA : MxOpModeEncoding<0b111>;
 // Encoding
 //===----------------------------------------------------------------------===//
 
-let Defs = [CCR] in {
+let Defs = [CCR, SR] in {
 let Constraints = "$src = $dst" in {
 
 /// Encoding for Normal forms
@@ -64,7 +64,7 @@ let Constraints = "$src = $dst" in {
 ///  x  x  x  x |   REG   | OP MODE |   MODE  |   REG
 /// ----------------------------------------------------
 
-// $reg, $ccr <- $reg op $reg
+// $reg, $ccr, $sr <- $reg op $reg
 class MxBiArOp_R_RR_xEA<string MN, SDNode NODE, MxType DST_TYPE, MxType SRC_TYPE,
                         bits<4> CMD>
     : MxInst<(outs DST_TYPE.ROp:$dst), (ins DST_TYPE.ROp:$src, SRC_TYPE.ROp:$opd),
@@ -190,7 +190,7 @@ class MxBiArOp_MI<string MN, MxType TYPE,
   );
 }
 } // mayLoad, mayStore
-} // Defs = [CCR]
+} // Defs = [CCR, SR]
 
 multiclass MxBiArOp_DF<string MN, SDNode NODE, bit isComm,
                        bits<4> CMD, bits<4> CMDI> {
@@ -319,7 +319,7 @@ defm SUB : MxBiArOp_AF<"suba", MxSub, 0x9>;
 //   t8: i32,i8 = ADD32ab GLOBAL_OFFSET_TABLE, TargetGlobalTLSAddress:i32<ptr @myvar>
 def : Pat<(add MxARD32:$src, tglobaltlsaddr:$opd), (ADD32ab MxARD32:$src, MxAL32:$opd)>;
 
-let Uses = [CCR], Defs = [CCR] in {
+let Uses = [CCR, SR], Defs = [CCR, SR] in {
 let Constraints = "$src = $dst" in {
 
 /// Encoding for Extended forms
@@ -394,7 +394,7 @@ defm XOR : MxBiArOp_DF_EAd<"eor", MxXor, 0xB, 0xA>;
 // CMP
 //===----------------------------------------------------------------------===//
 
-let Defs = [CCR] in {
+let Defs = [CCR, SR] in {
 class MxCmp_RR<MxType LHS_TYPE, MxType RHS_TYPE = LHS_TYPE>
     : MxInst<(outs), (ins LHS_TYPE.ROp:$lhs, RHS_TYPE.ROp:$rhs),
              "cmp."#RHS_TYPE.Prefix#"\t$lhs, $rhs",
@@ -480,7 +480,7 @@ class MxCmp_RM<MxType TYPE, MxOperand MEMOpd, ComplexPattern MEMPat,
 }
 } // let mayLoad = 1
 
-} // let Defs = [CCR]
+} // let Defs = [CCR, SR]
 
 multiclass MMxCmp_RM<MxType TYPE> {
   def NAME#TYPE.KOp.Letter : MxCmp_RM<TYPE, TYPE.KOp, TYPE.KPat, MxEncAddrMode_k<"mem">>;
@@ -534,7 +534,7 @@ defm CMP32 : MMxCmp_MI<MxType32d>;
 /// ---------------------------------------------------
 ///  0  1  0  0  1  0  0 |  OPMODE | 0  0  0 |   REG
 /// ---------------------------------------------------
-let Defs = [CCR] in
+let Defs = [CCR, SR] in
 let Constraints = "$src = $dst" in
 class MxExt<MxType TO, MxType FROM>
     : MxInst<(outs TO.ROp:$dst), (ins TO.ROp:$src),
@@ -575,7 +575,7 @@ def : Pat<(sext_inreg i32:$src, i8),
 ///             |         |         | EFFECTIVE ADDRESS
 ///  x  x  x  x |   REG   | OP MODE |   MODE  |   REG
 /// ----------------------------------------------------
-let Defs = [CCR] in {
+let Defs = [CCR, SR] in {
 let Constraints = "$src = $dst" in {
 // $dreg <- $dreg op $dreg
 class MxDiMuOp_DD<string MN, bits<4> CMD, bit SIGNED = false,
@@ -621,7 +621,7 @@ class MxDiMuOp_DI<string MN, bits<4> CMD, bit SIGNED = false,
   );
 }
 } // let Constraints
-} // Defs = [CCR]
+} // Defs = [CCR, SR]
 
 multiclass MxDiMuOp<string MN, bits<4> CMD> {
   def "S"#NAME#"d32d16" : MxDiMuOp_DD<MN#"s", CMD, /*SIGNED*/true, MxDRD32, MxDRD16>;
@@ -778,7 +778,7 @@ def : Pat<(mulhu i16:$dst, Mxi16immSExt16:$opd),
 ///             |            |      | EFFECTIVE ADDRESS
 ///  0  1  0  0 | x  x  x  x | SIZE |   MODE  |   REG
 /// ------------+------------+------+---------+---------
-let Defs = [CCR] in {
+let Defs = [CCR, SR] in {
 let Constraints = "$src = $dst" in {
 
 class MxNeg_D<MxType TYPE>
@@ -794,7 +794,7 @@ class MxNeg_D<MxType TYPE>
   );
 }
 
-let Uses = [CCR] in {
+let Uses = [CCR, SR] in {
 class MxNegX_D<MxType TYPE>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src),
              "negx."#TYPE.Prefix#"\t$dst",
@@ -823,7 +823,7 @@ class MxNot_D<MxType TYPE>
 }
 
 } // let Constraints
-} // let Defs = [CCR]
+} // let Defs = [CCR, SR]
 
 foreach S = [8, 16, 32] in {
   def NEG#S#d  : MxNeg_D<!cast<MxType>("MxType"#S#"d")>;
diff --git a/llvm/lib/Target/M68k/M68kInstrBits.td b/llvm/lib/Target/M68k/M68kInstrBits.td
index 55c95e467096a0..2f81072c91f6cb 100644
--- a/llvm/lib/Target/M68k/M68kInstrBits.td
+++ b/llvm/lib/Target/M68k/M68kInstrBits.td
@@ -57,7 +57,7 @@ class MxBITEnc_I<bits<3> opmode, MxEncMemOp dst_enc, string bitno_name> {
   );
 }
 
-let Defs = [CCR] in {
+let Defs = [CCR, SR] in {
 class MxBIT_RR<string MN, bits<3> OPMODE, MxType TYPE>
     : MxInst<(outs), (ins TYPE.ROp:$dst, TYPE.ROp:$bitno),
              MN#"\t$bitno, $dst"> {
@@ -83,7 +83,7 @@ class MxBIT_MI<string MN, bits<3> OPMODE, MxType TYPE,
              MN#"\t$bitno, $dst"> {
   let Inst = MxBITEnc_I<OPMODE, DST_ENC, "bitno">.Value;
 }
-} // Defs = [CCR]
+} // Defs = [CCR, SR]
 
 def BTST8qd : MxBIT_MR<"btst", 0b100, MxType8d, MxType8.QOp,
                         MxEncAddrMode_q<"dst">>;
diff --git a/llvm/lib/Target/M68k/M68kInstrCompiler.td b/llvm/lib/Target/M68k/M68kInstrCompiler.td
index 2ecf5ca0e6d0ef..fd805fbcc1565c 100644
--- a/llvm/lib/Target/M68k/M68kInstrCompiler.td
+++ b/llvm/lib/Target/M68k/M68kInstrCompiler.td
@@ -54,7 +54,7 @@ def : Pat<(i32 (MxWrapperPC tblockaddress :$src)), (LEA32q tblockaddress :$src)>
 // instruction selection into a branch sequence.
 //===----------------------------------------------------------------------===//
 
-let usesCustomInserter = 1, Uses = [CCR] in
+let usesCustomInserter = 1, Uses = [CCR, SR] in
 class MxCMove<MxType TYPE>
     : MxPseudo<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$t, TYPE.ROp:$f, i8imm:$cond),
                [(set TYPE.VT:$dst,
@@ -73,7 +73,7 @@ def CMOV32r : MxCMove<MxType32r>;
 // a stack adjustment and the codegen must know that they may modify the stack
 // pointer before prolog-epilog rewriting occurs.
 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
-// sub / add which can clobber CCR.
+// sub / add which can clobber CCR + SR.
 let Defs = [SP, CCR], Uses = [SP] in {
 
   def ADJCALLSTACKDOWN
diff --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td
index a7d7f1826f7f9f..048d45891efea4 100644
--- a/llvm/lib/Target/M68k/M68kInstrData.td
+++ b/llvm/lib/Target/M68k/M68kInstrData.td
@@ -102,7 +102,7 @@ defm Dst : MxMoveOperandEncodings<"dst">;
 
 defvar MxMoveSupportedAMs = ["o", "e", "k", "q", "f", "p", "b", "j"];
 
-let Defs = [CCR] in
+let Defs = [CCR, SR] in
 class MxMove<string size, dag outs, dag ins, list<dag> pattern, MxMoveEncoding enc>
     : MxInst<outs, ins, "move."#size#"\t$src, $dst", pattern> {
   let Inst = enc.Value;
@@ -254,7 +254,7 @@ def : Pat<(store   MxType32.BPat :$src, MxType32.JPat :$dst),
 /// ------------+---------+---+-----------------------
 
 // No pattern, as all immediate -> register moves are matched to the MOVI pseudo
-let Defs = [CCR] in
+let Defs = [CCR, SR] in
 def MOVQ : MxInst<(outs MxDRD32:$dst), (ins Mxi8imm:$imm),
                   "moveq\t$imm, $dst",
                   [(null_frag)]> {
@@ -372,18 +372,22 @@ def MOVM32mp_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.POp>;
 ///                               | EFFECTIVE ADDRESS
 ///  0  1  0  0  0  1  0  0  1  1 |   MODE  |   REG
 /// --------------------------------------------------
-let Defs = [CCR] in {
+let Defs = [CCR, SR] in {
 class MxMoveToCCR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
     : MxInst<(outs CCRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
   let Inst = (ascend
     (descend 0b0100010011, SRC_ENC.EA),
     SRC_ENC.Supplement
   );
+  let Predicates = [AtLeastM68010];
 }
 
 class MxMoveToCCRPseudo<MxOperand MEMOp>
-    : MxPseudo<(outs CCRC:$dst), (ins MEMOp:$src)>;
-} // let Defs = [CCR]
+    : MxPseudo<(outs CCRC:$dst), (ins MEMOp:$src)> {
+      let Predicates = [AtLeastM68010];
+    }
+
+} // let Defs = [CCR, SR]
 
 let mayLoad = 1 in
 foreach AM = MxMoveSupportedAMs in {
@@ -403,7 +407,7 @@ def MOV8cd  : MxMoveToCCRPseudo<MxOp8AddrMode_d.Op>;
 ///                               | EFFECTIVE ADDRESS
 ///  0  1  0  0  0  0  1  0  1  1 |   MODE  |   REG
 /// --------------------------------------------------
-let Uses = [CCR] in {
+let Uses = [CCR, SR] in {
 class MxMoveFromCCR_R
     : MxInst<(outs MxDRD16:$dst), (ins CCRC:$src), "move.w\t$src, $dst", []>,
       Requires<[ AtLeastM68010 ]> {
@@ -411,8 +415,7 @@ class MxMoveFromCCR_R
 }
 
 class MxMoveFromCCR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
-    : MxInst<(outs), (ins MEMOp:$dst, CCRC:$src), "move.w\t$src, $dst", []>,
-      Requires<[ AtLeastM68010 ]> {
+    : MxInst<(outs), (ins MEMOp:$dst, CCRC:$src), "move.w\t$src, $dst", []> {
   let Inst = (ascend
     (descend 0b0100001011, DST_ENC.EA),
     DST_ENC.Supplement
@@ -423,7 +426,7 @@ class MxMoveFromCCRPseudo<MxOperand MEMOp>
     : MxPseudo<(outs), (ins MEMOp:$dst, CCRC:$src)>;
 class MxMoveFromCCR_RPseudo<MxOperand MEMOp>
     : MxPseudo<(outs MEMOp:$dst), (ins CCRC:$src)>;
-} // let Uses = [CCR]
+} // let Uses = [CCR, SR]
 
 let mayStore = 1 in
 foreach AM = MxMoveSupportedAMs in {
@@ -447,7 +450,8 @@ def MOV8dc  : MxMoveFromCCR_RPseudo<MxOp8AddrMode_d.Op>;
 /// --------------------------------------------------
 let Defs = [SR] in {
 class MxMoveToSR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
-    : MxInst<(outs SRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
+    : MxInst<(outs SRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []>,
+      Requires<[ AtLeastM68000, AtMostM68000 ]> {
   let Inst = (ascend
     (descend 0b0100011011, SRC_ENC.EA),
     SRC_ENC.Supplement
@@ -473,13 +477,13 @@ def MOV16sd : MxMoveToSR<MxOp16AddrMode_d.Op, MxMoveSrcOpEnc_d>;
 let Uses = [SR] in {
 class MxMoveFromSR_R
     : MxInst<(outs MxDRD16:$dst), (ins SRC:$src), "move.w\t$src, $dst", []>,
-      Requires<[ AtLeastM68010 ]> {
+      Requires<[ AtLeastM68000, AtMostM68000 ]> {
   let Inst = (descend 0b0100000011, MxEncAddrMode_d<"dst">.EA);
 }
 
 class MxMoveFromSR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
     : MxInst<(outs), (ins MEMOp:$dst, SRC:$src), "move.w\t$src, $dst", []>,
-      Requires<[ AtLeastM68010 ]> {
+      Requires<[ AtLeastM68000, AtMostM68000 ]> {
   let Inst = (ascend
     (descend 0b0100000011, DST_ENC.EA),
     DST_ENC.Supplement
@@ -571,7 +575,7 @@ def POP32r : MxPseudo<(outs XR32:$reg), (ins)>;
 } // let Uses/Defs = [SP], hasSideEffects = 0
 
 
-let Defs = [CCR] in {
+let Defs = [CCR, SR] in {
 class MxPseudoMove_RR<MxType DST, MxType SRC, list<dag> PAT = []>
     : MxPseudo<(outs DST.ROp:$dst), (ins SRC.ROp:$src), PAT>;
 
@@ -593,7 +597,7 @@ class MxPseudoMove_DI<MxType TYPE>
 def MOVI8di  : MxPseudoMove_DI<MxType8d>;
 def MOVI16ri : MxPseudoMove_DI<MxType16r>;
 def MOVI32ri : MxPseudoMove_DI<MxType32r>;
-} // let Defs = [CCR]
+} // let Defs = [CCR, SR]
 
 /// This group of Pseudos is analogues to the real x86 extending moves, but
 /// since M68k does not have those we need to emulate. These instructions
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 63404645209508..e83f2a7d81f458 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -30,6 +30,7 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Regex.h"
 
+#include <algorithm>
 #include <functional>
 
 using namespace llvm;
@@ -759,6 +760,8 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   bool ToCCR = DstReg == M68k::CCR;
   bool ToSR = DstReg == M68k::SR;
 
+  assert((FromCCR+FromSR+ToCCR+ToSR) <= 1 && "Copies may only touch one of either SR or CCR");
+
   if (FromCCR) {
     if (M68k::DR8RegClass.contains(DstReg)) {
       Opc = M68k::MOV8dc;
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index dca774e94b9b5a..a21935e32dbed0 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -435,6 +435,10 @@ def AtLeastM68881 : Predicate<"Subtarget->atLeastM68881()">,
                     AssemblerPredicate<(all_of FeatureISA881)>;
 def AtLeastM68882 : Predicate<"Subtarget->atLeastM68882()">,
                     AssemblerPredicate<(all_of FeatureISA882)>;
+                    foreach i = [0,1,2,4,6] in
+def AtMostM680 # i # "0" : Predicate<"Subtarget->atMostM680"#i#"0()">,
+                            AssemblerPredicate<(all_of
+                                                !cast<SubtargetFeature>("FeatureISA"#i#"0"))>;
 
 //===----------------------------------------------------------------------===//
 // Condition Codes
diff --git a/llvm/lib/Target/M68k/M68kInstrShiftRotate.td b/llvm/lib/Target/M68k/M68kInstrShiftRotate.td
index 7de99462601442..3f9ff4a9428260 100644
--- a/llvm/lib/Target/M68k/M68kInstrShiftRotate.td
+++ b/llvm/lib/Target/M68k/M68kInstrShiftRotate.td
@@ -74,7 +74,7 @@ class MxSR_DI<string MN, MxType TYPE, SDNode NODE, bit RODI, bits<2> ROOP>
 
 multiclass MxSROp<string MN, SDNode NODE, bit RODI, bits<2> ROOP> {
 
-  let Defs = [CCR] in {
+  let Defs = [CCR, SR] in {
   let Constraints = "$src = $dst" in {
 
   def NAME#"8dd"  : MxSR_DD<MN, MxType8d,  NODE, RODI, ROOP>;
@@ -86,7 +86,7 @@ multiclass MxSROp<string MN, SDNode NODE, bit RODI, bits<2> ROOP> {
   def NAME#"32di" : MxSR_DI<MN, MxType32d, NODE, RODI, ROOP>;
 
   } // $src = $dst
-  } // Defs = [CCR]
+  } // Defs = [CCR, SR]
 
 } // MxBiArOp_RF
 
diff --git a/llvm/lib/Target/M68k/M68kRegisterInfo.td b/llvm/lib/Target/M68k/M68kRegisterInfo.td
index 45b492eba4ec07..d1ccca5dcba67f 100644
--- a/llvm/lib/Target/M68k/M68kRegisterInfo.td
+++ b/llvm/lib/Target/M68k/M68kRegisterInfo.td
@@ -87,7 +87,7 @@ class MxPseudoReg<string N, list<Register> SUBREGS = [], list<SubRegIndex> SUBID
     : MxReg<N, 0, SUBREGS, SUBIDX>;
 
 def CCR : MxPseudoReg<"ccr">;
-def SR  : MxPseudoReg<"sr">;
+def SR  : MxPseudoReg<"sr", [CCR], [SubRegIndex<16, 0>]>;
 
 def PC  : MxPseudoReg<"pc">;
 
diff --git a/llvm/lib/Target/M68k/M68kSubtarget.h b/llvm/lib/Target/M68k/M68kSubtarget.h
index c08a9786fb27ba..4fa526aa84ed06 100644
--- a/llvm/lib/Target/M68k/M68kSubtarget.h
+++ b/llvm/lib/Target/M68k/M68kSubtarget.h
@@ -91,6 +91,13 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
   bool atLeastM68040() const { return SubtargetKind >= M40; }
   bool atLeastM68060() const { return SubtargetKind >= M60; }
 
+  bool atMostM68000() const { return SubtargetKind <= M00; }
+  bool atMostM68010() const { return SubtargetKind <= M10; }
+  bool atMostM68020() const { return SubtargetKind <= M20; }
+  bool atMostM68030() const { return SubtargetKind <= M30; }
+  bool atMostM68040() const { return SubtargetKind <= M40; }
+  bool atMostM68060() const { return SubtargetKind <= M60; }
+
   /// Floating point support
   bool hasFPU() const { return FPUKind.has_value(); }
   bool atLeastM68881() const { return hasFPU() && *FPUKind >= M881; }
diff --git a/llvm/test/CodeGen/M68k/CConv/rtd-call.ll b/llvm/test/CodeGen/M68k/CConv/rtd-call.ll
index 56f36efbe0fb96..094932bb53bea2 100644
--- a/llvm/test/CodeGen/M68k/CConv/rtd-call.ll
+++ b/llvm/test/CodeGen/M68k/CConv/rtd-call.ll
@@ -13,11 +13,11 @@ declare dso_local m68k_rtdcc void @va_callee(i32 noundef, ...)
 define dso_local i32 @caller(ptr noundef %y) {
   ; CHECK-LABEL: name: caller
   ; CHECK: bb.0.entry:
-  ; CHECK-NEXT:   [[MOV32rp:%[0-9]+]]:ar32 = MOV32rp 0, %fixed-stack.0, implicit-def dead $ccr :: (load (s32) from %fixed-stack.0, align 8)
-  ; CHECK-NEXT:   [[MOV32rj:%[0-9]+]]:xr32 = MOV32rj killed [[MOV32rp]], implicit-def dead $ccr :: (load (s32) from %ir.y)
+  ; CHECK-NEXT:   [[MOV32rp:%[0-9]+]]:ar32 = MOV32rp 0, %fixed-stack.0, implicit-def dead $ccr, implicit-def dead $sr :: (load (s32) from %fixed-stack.0, align 8)
+  ; CHECK-NEXT:   [[MOV32rj:%[0-9]+]]:xr32 = MOV32rj killed [[MOV32rp]], implicit-def dead $ccr, implicit-def dead $sr :: (load (s32) from %ir.y)
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 4, 0, implicit-def dead $sp, implicit-def dead $ccr, implicit $sp
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:ar32 = COPY $sp
-  ; CHECK-NEXT:   MOV32jr [[COPY]], [[MOV32rj]], implicit-def dead $ccr :: (store (s32) into stack, align 2)
+  ; CHECK-NEXT:   MOV32jr [[COPY]], [[MOV32rj]], implicit-def dead $ccr, implicit-def dead $sr :: (store (s32) into stack, align 2)
   ; CHECK-NEXT:   CALLb @callee, csr_std, implicit $sp, implicit-def $sp
   ; CHECK-NEXT:   ADJCALLSTACKUP 4, 4, implicit-def dead $sp, implicit-def dead $ccr, implicit $sp
   ; CHECK-NEXT:   $d0 = COPY [[MOV32rj]]
@@ -31,11 +31,11 @@ entry:
 define dso_local i32 @va_caller(ptr noundef %y) {
   ; CHECK-LABEL: name: va_caller
   ; CHECK: bb.0.entry:
-  ; CHECK-NEXT:   [[MOV32rp:%[0-9]+]]:ar32 = MOV32rp 0, %fixed-stack.0, implicit-def dead $ccr :: (load (s32) from %fixed-stack.0, align 8)
-  ; CHECK-NEXT:   [[MOV32rj:%[0-9]+]]:xr32 = MOV32rj killed [[MOV32rp]], implicit-def dead $ccr :: (load (s32) from %ir.y)
+  ; CHECK-NEXT:   [[MOV32rp:%[0-9]+]]:ar32 = MOV32rp 0, %fixed-stack.0, implicit-def dead $ccr, implicit-def dead $sr :: (load (s32) from %fixed-stack.0, align 8)
+  ; CHECK-NEXT:   [[MOV32rj:%[0-9]+]]:xr32 = MOV32rj killed [[MOV32rp]], implicit-def dead $ccr, implicit-def dead $sr :: (load (s32) from %ir.y)
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 4, 0, implicit-def dead $sp, implicit-def dead $ccr, implicit $sp
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:ar32 = COPY $sp
-  ; CHECK-NEXT:   MOV32jr [[COPY]], [[MOV32rj]], implicit-def dead $ccr :: (store (s32) into stack, align 2)
+  ; CHECK-NEXT:   MOV32jr [[COPY]], [[MOV32rj]], implicit-def dead $ccr, implicit-def dead $sr :: (store (s32) into stack, align 2)
   ; CHECK-NEXT:   CALLb @va_callee, csr_std, implicit $sp, implicit-def $sp
   ; CHECK-NEXT:   ADJCALLSTACKUP 4, 0, implicit-def dead $sp, implicit-def dead $ccr, implicit $sp
   ; CHECK-NEXT:   $d0 = COPY [[MOV32rj]]
diff --git a/llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir b/llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir
index a755164937b160..000726aec24fca 100644
--- a/llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir
+++ b/llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir
@@ -6,5 +6,5 @@ body:             |
     ; CHECK: move.l  (0,%pc,%a0), (%a1)
     ; CHECK: move.l  (%a0), (0,%pc,%a1)
 
-    MOV32jk $a1,  0, $a0, implicit-def $ccr
-    MOV32kj 0,  $a1, $a0, implicit-def $ccr
\ No newline at end of file
+    MOV32jk $a1,  0, $a0, implicit-def $ccr, implicit-def $sr
+    MOV32kj 0,  $a1, $a0, implicit-def $ccr, implicit-def $sr
\ No newline at end of file



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