[llvm] [InstCombine] fold unsigned predicates on srem result (PR #122520)
Jacob Young via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 12 04:47:35 PST 2025
https://github.com/jacobly0 updated https://github.com/llvm/llvm-project/pull/122520
>From 00085c711982108559874dae4b5335e329732a31 Mon Sep 17 00:00:00 2001
From: Jacob Young <jacobly0 at users.noreply.github.com>
Date: Sun, 12 Jan 2025 06:58:48 -0500
Subject: [PATCH 1/2] [InstCombine][NFC] precommit tests for signed floor
division
---
llvm/test/Transforms/InstCombine/add.ll | 34 ++++
llvm/test/Transforms/InstCombine/icmp-srem.ll | 146 ++++++++++++++++++
2 files changed, 180 insertions(+)
create mode 100644 llvm/test/Transforms/InstCombine/icmp-srem.ll
diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index 222f87fa3a5f18..5684bee06b9164 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -3018,6 +3018,40 @@ define i32 @floor_sdiv_wrong_op(i32 %x, i32 %y) {
ret i32 %r
}
+define i32 @floor_sdiv_using_srem_by_8(i32 %x) {
+; CHECK-LABEL: @floor_sdiv_using_srem_by_8(
+; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 8
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 8
+; CHECK-NEXT: [[I:%.*]] = icmp ugt i32 [[R]], -2147483648
+; CHECK-NEXT: [[S:%.*]] = sext i1 [[I]] to i32
+; CHECK-NEXT: [[F:%.*]] = add nsw i32 [[D]], [[S]]
+; CHECK-NEXT: ret i32 [[F]]
+;
+ %d = sdiv i32 %x, 8
+ %r = srem i32 %x, 8
+ %i = icmp ugt i32 %r, -2147483648
+ %s = sext i1 %i to i32
+ %f = add i32 %d, %s
+ ret i32 %f
+}
+
+define i32 @floor_sdiv_using_srem_by_2(i32 %x) {
+; CHECK-LABEL: @floor_sdiv_using_srem_by_2(
+; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 2
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 2
+; CHECK-NEXT: [[I:%.*]] = icmp ugt i32 [[R]], -2147483648
+; CHECK-NEXT: [[S:%.*]] = sext i1 [[I]] to i32
+; CHECK-NEXT: [[F:%.*]] = add nsw i32 [[D]], [[S]]
+; CHECK-NEXT: ret i32 [[F]]
+;
+ %d = sdiv i32 %x, 2
+ %r = srem i32 %x, 2
+ %i = icmp ugt i32 %r, -2147483648
+ %s = sext i1 %i to i32
+ %f = add i32 %d, %s
+ ret i32 %f
+}
+
; (X s>> (BW - 1)) + (zext (X s> 0)) --> (X s>> (BW - 1)) | (zext (X != 0))
define i8 @signum_i8_i8(i8 %x) {
diff --git a/llvm/test/Transforms/InstCombine/icmp-srem.ll b/llvm/test/Transforms/InstCombine/icmp-srem.ll
new file mode 100644
index 00000000000000..bb8f0f60db793c
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/icmp-srem.ll
@@ -0,0 +1,146 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i1 @icmp_ugt_srem5_smin(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ugt_srem5_smin(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], -2147483648
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ugt i32 %r, -2147483648
+ ret i1 %c
+}
+
+define i1 @icmp_ugt_srem5_m5(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ugt_srem5_m5(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], -5
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ugt i32 %r, -5
+ ret i1 %c
+}
+
+define i1 @icmp_ugt_srem5_m4(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ugt_srem5_m4(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], -4
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ugt i32 %r, -4
+ ret i1 %c
+}
+
+define i1 @icmp_ugt_srem5_3(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ugt_srem5_3(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], 3
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ugt i32 %r, 3
+ ret i1 %c
+}
+
+define i1 @icmp_ugt_srem5_4(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ugt_srem5_4(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], 4
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ugt i32 %r, 4
+ ret i1 %c
+}
+
+define i1 @icmp_ugt_srem5_smaxm1(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ugt_srem5_smaxm1(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], 2147483646
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ugt i32 %r, 2147483646
+ ret i1 %c
+}
+
+define i1 @icmp_ult_srem5_sminp1(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ult_srem5_sminp1(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], -2147483647
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ult i32 %r, -2147483647
+ ret i1 %c
+}
+
+define i1 @icmp_ult_srem5_m4(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ult_srem5_m4(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], -4
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ult i32 %r, -4
+ ret i1 %c
+}
+
+define i1 @icmp_ult_srem5_m3(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ult_srem5_m3(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], -3
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ult i32 %r, -3
+ ret i1 %c
+}
+
+define i1 @icmp_ult_srem5_4(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ult_srem5_4(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], 4
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ult i32 %r, 4
+ ret i1 %c
+}
+
+define i1 @icmp_ult_srem5_5(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ult_srem5_5(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], 5
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ult i32 %r, 5
+ ret i1 %c
+}
+
+define i1 @icmp_ult_srem5_smax(i32 %x) {
+; CHECK-LABEL: define i1 @icmp_ult_srem5_smax(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], 2147483647
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %r = srem i32 %x, 5
+ %c = icmp ult i32 %r, 2147483647
+ ret i1 %c
+}
>From e15c88e613f32a0bfc36a641206605dae4873645 Mon Sep 17 00:00:00 2001
From: Jacob Young <jacobly0 at users.noreply.github.com>
Date: Sun, 12 Jan 2025 07:01:25 -0500
Subject: [PATCH 2/2] [InstCombine] fold unsigned predicates to signed on srem
result
This allows optimization of more signed floor implementations when the
divisor is a known power of two to an arithmetic shift.
Proof for the implemented optimizations:
https://alive2.llvm.org/ce/z/j6C-Nz
Proof for the test cases:
https://alive2.llvm.org/ce/z/M_PBjw
---
.../InstCombine/InstCombineCompares.cpp | 33 ++++++++++++++++++-
llvm/test/Transforms/InstCombine/add.ll | 12 ++-----
llvm/test/Transforms/InstCombine/icmp-srem.ll | 16 ++++-----
3 files changed, 42 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 2e457257599493..c107a12fcf4324 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -2674,10 +2674,41 @@ Instruction *InstCombinerImpl::foldICmpShrConstant(ICmpInst &Cmp,
Instruction *InstCombinerImpl::foldICmpSRemConstant(ICmpInst &Cmp,
BinaryOperator *SRem,
const APInt &C) {
+ const ICmpInst::Predicate Pred = Cmp.getPredicate();
+ if (Pred == ICmpInst::ICMP_UGT || Pred == ICmpInst::ICMP_ULT) {
+ // Canonicalize unsigned predicates to signed:
+ // (X % DivisorC) ugt C -> (X % DivisorC) slt 0
+ // iff (C slt 0 ? ~C : C) uge abs(DivisorC)-1
+ // (X % DivisorC) ult C+1 -> (X % DivisorC) sgt -1
+ // iff (C+1 slt 0 ? ~C : C) uge abs(DivisorC)-1
+
+ const APInt *DivisorC;
+ if (!match(SRem->getOperand(1), m_APInt(DivisorC)))
+ return nullptr;
+
+ APInt NormalizedC = C;
+ if (Pred == ICmpInst::ICMP_ULT) {
+ assert(!NormalizedC.isZero() &&
+ "ult X, 0 should have been simplified already.");
+ --NormalizedC;
+ }
+ if (C.isNegative())
+ NormalizedC.flipAllBits();
+ assert(!DivisorC->isZero() &&
+ "srem X, 0 should have been simplified already.");
+ if (!NormalizedC.uge(DivisorC->abs() - 1))
+ return nullptr;
+
+ Type *Ty = SRem->getType();
+ if (Pred == ICmpInst::ICMP_UGT)
+ return new ICmpInst(ICmpInst::ICMP_SLT, SRem,
+ ConstantInt::getNullValue(Ty));
+ return new ICmpInst(ICmpInst::ICMP_SGT, SRem,
+ ConstantInt::getAllOnesValue(Ty));
+ }
// Match an 'is positive' or 'is negative' comparison of remainder by a
// constant power-of-2 value:
// (X % pow2C) sgt/slt 0
- const ICmpInst::Predicate Pred = Cmp.getPredicate();
if (Pred != ICmpInst::ICMP_SGT && Pred != ICmpInst::ICMP_SLT &&
Pred != ICmpInst::ICMP_EQ && Pred != ICmpInst::ICMP_NE)
return nullptr;
diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index 5684bee06b9164..495f99824652d6 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -3020,11 +3020,7 @@ define i32 @floor_sdiv_wrong_op(i32 %x, i32 %y) {
define i32 @floor_sdiv_using_srem_by_8(i32 %x) {
; CHECK-LABEL: @floor_sdiv_using_srem_by_8(
-; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 8
-; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 8
-; CHECK-NEXT: [[I:%.*]] = icmp ugt i32 [[R]], -2147483648
-; CHECK-NEXT: [[S:%.*]] = sext i1 [[I]] to i32
-; CHECK-NEXT: [[F:%.*]] = add nsw i32 [[D]], [[S]]
+; CHECK-NEXT: [[F:%.*]] = ashr i32 [[X:%.*]], 3
; CHECK-NEXT: ret i32 [[F]]
;
%d = sdiv i32 %x, 8
@@ -3037,11 +3033,7 @@ define i32 @floor_sdiv_using_srem_by_8(i32 %x) {
define i32 @floor_sdiv_using_srem_by_2(i32 %x) {
; CHECK-LABEL: @floor_sdiv_using_srem_by_2(
-; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 2
-; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 2
-; CHECK-NEXT: [[I:%.*]] = icmp ugt i32 [[R]], -2147483648
-; CHECK-NEXT: [[S:%.*]] = sext i1 [[I]] to i32
-; CHECK-NEXT: [[F:%.*]] = add nsw i32 [[D]], [[S]]
+; CHECK-NEXT: [[F:%.*]] = ashr i32 [[X:%.*]], 1
; CHECK-NEXT: ret i32 [[F]]
;
%d = sdiv i32 %x, 2
diff --git a/llvm/test/Transforms/InstCombine/icmp-srem.ll b/llvm/test/Transforms/InstCombine/icmp-srem.ll
index bb8f0f60db793c..8b3aac8f5b1fda 100644
--- a/llvm/test/Transforms/InstCombine/icmp-srem.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-srem.ll
@@ -5,7 +5,7 @@ define i1 @icmp_ugt_srem5_smin(i32 %x) {
; CHECK-LABEL: define i1 @icmp_ugt_srem5_smin(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
-; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], -2147483648
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[R]], 0
; CHECK-NEXT: ret i1 [[C]]
;
%r = srem i32 %x, 5
@@ -17,7 +17,7 @@ define i1 @icmp_ugt_srem5_m5(i32 %x) {
; CHECK-LABEL: define i1 @icmp_ugt_srem5_m5(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
-; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], -5
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[R]], 0
; CHECK-NEXT: ret i1 [[C]]
;
%r = srem i32 %x, 5
@@ -53,7 +53,7 @@ define i1 @icmp_ugt_srem5_4(i32 %x) {
; CHECK-LABEL: define i1 @icmp_ugt_srem5_4(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
-; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], 4
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[R]], 0
; CHECK-NEXT: ret i1 [[C]]
;
%r = srem i32 %x, 5
@@ -65,7 +65,7 @@ define i1 @icmp_ugt_srem5_smaxm1(i32 %x) {
; CHECK-LABEL: define i1 @icmp_ugt_srem5_smaxm1(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
-; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], 2147483646
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[R]], 0
; CHECK-NEXT: ret i1 [[C]]
;
%r = srem i32 %x, 5
@@ -77,7 +77,7 @@ define i1 @icmp_ult_srem5_sminp1(i32 %x) {
; CHECK-LABEL: define i1 @icmp_ult_srem5_sminp1(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
-; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], -2147483647
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[R]], -1
; CHECK-NEXT: ret i1 [[C]]
;
%r = srem i32 %x, 5
@@ -89,7 +89,7 @@ define i1 @icmp_ult_srem5_m4(i32 %x) {
; CHECK-LABEL: define i1 @icmp_ult_srem5_m4(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
-; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], -4
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[R]], -1
; CHECK-NEXT: ret i1 [[C]]
;
%r = srem i32 %x, 5
@@ -125,7 +125,7 @@ define i1 @icmp_ult_srem5_5(i32 %x) {
; CHECK-LABEL: define i1 @icmp_ult_srem5_5(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
-; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], 5
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[R]], -1
; CHECK-NEXT: ret i1 [[C]]
;
%r = srem i32 %x, 5
@@ -137,7 +137,7 @@ define i1 @icmp_ult_srem5_smax(i32 %x) {
; CHECK-LABEL: define i1 @icmp_ult_srem5_smax(
; CHECK-SAME: i32 [[X:%.*]]) {
; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
-; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], 2147483647
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[R]], -1
; CHECK-NEXT: ret i1 [[C]]
;
%r = srem i32 %x, 5
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