[llvm] [InstCombine] Remove `sub nuw C_Mask, X` -> `xor X, C_Mask` canoncalization (PR #122607)

[via llvm-commits]

https://github.com/goldsteinn created https://github.com/llvm/llvm-project/pull/122607

None

>From b6bba9ea2ce017348ea1f6a51ef0e83b3d182adb Mon Sep 17 00:00:00 2001
From: Noah Goldstein <goldstein.w.n at gmail.com>
Date: Sat, 11 Jan 2025 13:01:56 -0600
Subject: [PATCH] [InstCombine] Remove `sub nuw C_Mask, X` -> `xor X, C_Mask`
 canoncalization

---
 llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | 10 ----------
 llvm/test/Transforms/InstCombine/sub-xor.ll           |  6 +++---
 2 files changed, 3 insertions(+), 13 deletions(-)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index 73876d00e73a7c..b253af0a828b61 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -2424,16 +2424,6 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
 
   const APInt *Op0C;
   if (match(Op0, m_APInt(Op0C))) {
-    if (Op0C->isMask()) {
-      // Turn this into a xor if LHS is 2^n-1 and the remaining bits are known
-      // zero. We don't use information from dominating conditions so this
-      // transform is easier to reverse if necessary.
-      KnownBits RHSKnown = llvm::computeKnownBits(
-          Op1, 0, SQ.getWithInstruction(&I).getWithoutDomCondCache());
-      if ((*Op0C | RHSKnown.Zero).isAllOnes())
-        return BinaryOperator::CreateXor(Op1, Op0);
-    }
-
     // C - ((C3 -nuw X) & C2) --> (C - (C2 & C3)) + (X & C2) when:
     // (C3 - ((C2 & C3) - 1)) is pow2
     // ((C2 + C3) & ((C2 & C3) - 1)) == ((C2 & C3) - 1)
diff --git a/llvm/test/Transforms/InstCombine/sub-xor.ll b/llvm/test/Transforms/InstCombine/sub-xor.ll
index a4135e0b514532..dc2113de546e51 100644
--- a/llvm/test/Transforms/InstCombine/sub-xor.ll
+++ b/llvm/test/Transforms/InstCombine/sub-xor.ll
@@ -6,7 +6,7 @@ declare void @use(i32)
 define i32 @low_mask_nsw_nuw(i32 %x) {
 ; CHECK-LABEL: @low_mask_nsw_nuw(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 31
-; CHECK-NEXT:    [[SUB:%.*]] = xor i32 [[AND]], 63
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 63, [[AND]]
 ; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %and = and i32 %x, 31
@@ -17,7 +17,7 @@ define i32 @low_mask_nsw_nuw(i32 %x) {
 define <2 x i32> @low_mask_nsw_nuw_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @low_mask_nsw_nuw_vec(
 ; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 31)
-; CHECK-NEXT:    [[SUB:%.*]] = xor <2 x i32> [[AND]], splat (i32 63)
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw <2 x i32> splat (i32 63), [[AND]]
 ; CHECK-NEXT:    ret <2 x i32> [[SUB]]
 ;
   %and = and <2 x i32> %x, <i32 31, i32 31>
@@ -98,7 +98,7 @@ declare i32 @llvm.ctlz.i32(i32, i1)
 define i32 @range_masked_sub(i32 %x) {
 ; CHECK-LABEL: @range_masked_sub(
 ; CHECK-NEXT:    [[COUNT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true) #[[ATTR1:[0-9]+]]
-; CHECK-NEXT:    [[SUB:%.*]] = xor i32 [[COUNT]], 31
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 31, [[COUNT]]
 ; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %count = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) nounwind readnone