[llvm] [X86] X86FixupVectorConstantsPass - use VPMOVSX/ZX extensions for PS/PD domain moves (PR #122601)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 11 08:44:39 PST 2025
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/122601
For targets with free domain moves, or AVX512 support, allow the use of VPMOVSX/ZX extension loads to reduce the load sizes.
I've limited this to extension to i32/i64 types as we're mostly interested in shuffle mask loading here, but we could include i16 types as well just as easily.
Inspired by a regression on #122485
>From d2bb74144111e46b78c80692e643dfa5be362da8 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Sat, 11 Jan 2025 16:43:08 +0000
Subject: [PATCH] [X86] X86FixupVectorConstantsPass - use VPMOVSX/ZX extensions
for PS/PD domain moves
For targets with free domain moves, or AVX512 support, allow the use of VPMOVSX/ZX extension loads to reduce the load sizes.
I've limited this to extension to i32/i64 types as we're mostly interested in shuffle mask loading here, but we could include i16 types as well just as easily.
---
.../Target/X86/X86FixupVectorConstants.cpp | 119 +-
llvm/test/CodeGen/X86/avx512-build-vector.ll | 2 +-
llvm/test/CodeGen/X86/avx512-mask-op.ll | 4 +-
.../X86/avx512-shuffles/partial_permute.ll | 215 ++--
.../CodeGen/X86/avx512-shuffles/permute.ll | 144 +--
llvm/test/CodeGen/X86/avx512vl-intrinsics.ll | 12 +-
llvm/test/CodeGen/X86/combine-or.ll | 15 +-
llvm/test/CodeGen/X86/combine-sub-usat.ll | 36 +-
.../CodeGen/X86/expand-vp-cast-intrinsics.ll | 2 +-
llvm/test/CodeGen/X86/extract-concat.ll | 4 +-
.../X86/insert-into-constant-vector.ll | 4 +-
llvm/test/CodeGen/X86/isel-buildvector-avx.ll | 13 +-
llvm/test/CodeGen/X86/matrix-multiply.ll | 8 +-
llvm/test/CodeGen/X86/nontemporal-4.ll | 32 +-
llvm/test/CodeGen/X86/pr29112.ll | 20 +-
llvm/test/CodeGen/X86/pr46532.ll | 2 +-
llvm/test/CodeGen/X86/pr78109.ll | 8 +-
llvm/test/CodeGen/X86/pr97968.ll | 3 +-
llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll | 12 +-
llvm/test/CodeGen/X86/vec_fp_to_int.ll | 182 ++-
llvm/test/CodeGen/X86/vec_minmax_sint.ll | 288 ++++-
llvm/test/CodeGen/X86/vec_minmax_uint.ll | 288 ++++-
llvm/test/CodeGen/X86/vector-compress.ll | 18 +-
.../CodeGen/X86/vector-half-conversions.ll | 4 +-
.../vector-interleaved-load-i32-stride-6.ll | 32 +-
.../vector-interleaved-load-i64-stride-3.ll | 8 +-
.../vector-interleaved-load-i64-stride-4.ll | 8 +-
.../vector-interleaved-store-i32-stride-2.ll | 32 +-
.../vector-interleaved-store-i32-stride-3.ll | 32 +-
.../vector-interleaved-store-i32-stride-4.ll | 24 +-
.../vector-interleaved-store-i32-stride-5.ll | 16 +-
.../vector-interleaved-store-i32-stride-6.ll | 16 +-
.../vector-interleaved-store-i64-stride-2.ll | 16 +-
.../vector-interleaved-store-i64-stride-3.ll | 16 +-
llvm/test/CodeGen/X86/vector-lzcnt-128.ll | 80 +-
llvm/test/CodeGen/X86/vector-lzcnt-256.ll | 112 +-
llvm/test/CodeGen/X86/vector-popcnt-128.ll | 44 +-
llvm/test/CodeGen/X86/vector-popcnt-256.ll | 76 +-
.../test/CodeGen/X86/vector-shuffle-128-v4.ll | 4 +-
.../test/CodeGen/X86/vector-shuffle-256-v4.ll | 20 +-
.../test/CodeGen/X86/vector-shuffle-256-v8.ll | 512 +++++---
.../CodeGen/X86/vector-shuffle-512-v16.ll | 24 +-
.../CodeGen/X86/vector-shuffle-512-v64.ll | 2 +-
.../test/CodeGen/X86/vector-shuffle-512-v8.ll | 1032 ++++++-----------
.../test/CodeGen/X86/vector-shuffle-avx512.ll | 27 +-
.../X86/vector-shuffle-combining-avx.ll | 27 +-
.../X86/vector-shuffle-combining-avx2.ll | 47 +-
.../X86/vector-shuffle-combining-avx512f.ll | 106 +-
llvm/test/CodeGen/X86/vector-tzcnt-128.ll | 124 +-
llvm/test/CodeGen/X86/vector-tzcnt-256.ll | 172 ++-
llvm/test/CodeGen/X86/vselect-avx.ll | 2 +-
llvm/test/CodeGen/X86/widen_fadd.ll | 2 +-
llvm/test/CodeGen/X86/widen_fdiv.ll | 2 +-
llvm/test/CodeGen/X86/widen_fmul.ll | 2 +-
llvm/test/CodeGen/X86/widen_fsub.ll | 2 +-
.../CodeGen/X86/x86-interleaved-access.ll | 4 +-
56 files changed, 2352 insertions(+), 1706 deletions(-)
diff --git a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
index 68a4a0be3a1db7..7390cc58054528 100644
--- a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
+++ b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp
@@ -338,6 +338,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
bool HasDQI = ST->hasDQI();
bool HasBWI = ST->hasBWI();
bool HasVLX = ST->hasVLX();
+ bool MultiDomain = ST->hasAVX512() || ST->hasNoDomainDelayMov();
struct FixupEntry {
int Op;
@@ -401,47 +402,107 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
case X86::VMOVAPDrm:
case X86::VMOVAPSrm:
case X86::VMOVUPDrm:
- case X86::VMOVUPSrm:
- return FixupConstant({{X86::VMOVSSrm, 1, 32, rebuildZeroUpperCst},
- {X86::VBROADCASTSSrm, 1, 32, rebuildSplatCst},
- {X86::VMOVSDrm, 1, 64, rebuildZeroUpperCst},
- {X86::VMOVDDUPrm, 1, 64, rebuildSplatCst}},
- 128, 1);
+ case X86::VMOVUPSrm: {
+ FixupEntry Fixups[] = {
+ {MultiDomain ? X86::VPMOVSXBQrm : 0, 2, 8, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXBQrm : 0, 2, 8, rebuildZExtCst},
+ {X86::VMOVSSrm, 1, 32, rebuildZeroUpperCst},
+ {X86::VBROADCASTSSrm, 1, 32, rebuildSplatCst},
+ {MultiDomain ? X86::VPMOVSXBDrm : 0, 4, 8, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXBDrm : 0, 4, 8, rebuildZExtCst},
+ {MultiDomain ? X86::VPMOVSXWQrm : 0, 2, 16, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXWQrm : 0, 2, 16, rebuildZExtCst},
+ {X86::VMOVSDrm, 1, 64, rebuildZeroUpperCst},
+ {X86::VMOVDDUPrm, 1, 64, rebuildSplatCst},
+ {MultiDomain ? X86::VPMOVSXWDrm : 0, 4, 16, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXWDrm : 0, 4, 16, rebuildZExtCst},
+ {MultiDomain ? X86::VPMOVSXDQrm : 0, 2, 32, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXDQrm : 0, 2, 32, rebuildZExtCst}};
+ return FixupConstant(Fixups, 128, 1);
+ }
case X86::VMOVAPDYrm:
case X86::VMOVAPSYrm:
case X86::VMOVUPDYrm:
- case X86::VMOVUPSYrm:
- return FixupConstant({{X86::VBROADCASTSSYrm, 1, 32, rebuildSplatCst},
- {X86::VBROADCASTSDYrm, 1, 64, rebuildSplatCst},
- {X86::VBROADCASTF128rm, 1, 128, rebuildSplatCst}},
- 256, 1);
+ case X86::VMOVUPSYrm: {
+ FixupEntry Fixups[] = {
+ {X86::VBROADCASTSSYrm, 1, 32, rebuildSplatCst},
+ {HasAVX2 && MultiDomain ? X86::VPMOVSXBQYrm : 0, 4, 8, rebuildSExtCst},
+ {HasAVX2 && MultiDomain ? X86::VPMOVZXBQYrm : 0, 4, 8, rebuildZExtCst},
+ {X86::VBROADCASTSDYrm, 1, 64, rebuildSplatCst},
+ {HasAVX2 && MultiDomain ? X86::VPMOVSXBDYrm : 0, 8, 8, rebuildSExtCst},
+ {HasAVX2 && MultiDomain ? X86::VPMOVZXBDYrm : 0, 8, 8, rebuildZExtCst},
+ {HasAVX2 && MultiDomain ? X86::VPMOVSXWQYrm : 0, 4, 16, rebuildSExtCst},
+ {HasAVX2 && MultiDomain ? X86::VPMOVZXWQYrm : 0, 4, 16, rebuildZExtCst},
+ {X86::VBROADCASTF128rm, 1, 128, rebuildSplatCst},
+ {HasAVX2 && MultiDomain ? X86::VPMOVSXWDYrm : 0, 8, 16, rebuildSExtCst},
+ {HasAVX2 && MultiDomain ? X86::VPMOVZXWDYrm : 0, 8, 16, rebuildZExtCst},
+ {HasAVX2 && MultiDomain ? X86::VPMOVSXDQYrm : 0, 4, 32, rebuildSExtCst},
+ {HasAVX2 && MultiDomain ? X86::VPMOVZXDQYrm : 0, 4, 32,
+ rebuildZExtCst}};
+ return FixupConstant(Fixups, 256, 1);
+ }
case X86::VMOVAPDZ128rm:
case X86::VMOVAPSZ128rm:
case X86::VMOVUPDZ128rm:
- case X86::VMOVUPSZ128rm:
- return FixupConstant({{X86::VMOVSSZrm, 1, 32, rebuildZeroUpperCst},
- {X86::VBROADCASTSSZ128rm, 1, 32, rebuildSplatCst},
- {X86::VMOVSDZrm, 1, 64, rebuildZeroUpperCst},
- {X86::VMOVDDUPZ128rm, 1, 64, rebuildSplatCst}},
- 128, 1);
+ case X86::VMOVUPSZ128rm: {
+ FixupEntry Fixups[] = {
+ {MultiDomain ? X86::VPMOVSXBQZ128rm : 0, 2, 8, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXBQZ128rm : 0, 2, 8, rebuildZExtCst},
+ {X86::VMOVSSZrm, 1, 32, rebuildZeroUpperCst},
+ {X86::VBROADCASTSSZ128rm, 1, 32, rebuildSplatCst},
+ {MultiDomain ? X86::VPMOVSXBDZ128rm : 0, 4, 8, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXBDZ128rm : 0, 4, 8, rebuildZExtCst},
+ {MultiDomain ? X86::VPMOVSXWQZ128rm : 0, 2, 16, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXWQZ128rm : 0, 2, 16, rebuildZExtCst},
+ {X86::VMOVSDZrm, 1, 64, rebuildZeroUpperCst},
+ {X86::VMOVDDUPZ128rm, 1, 64, rebuildSplatCst},
+ {MultiDomain ? X86::VPMOVSXWDZ128rm : 0, 4, 16, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXWDZ128rm : 0, 4, 16, rebuildZExtCst},
+ {MultiDomain ? X86::VPMOVSXDQZ128rm : 0, 2, 32, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXDQZ128rm : 0, 2, 32, rebuildZExtCst}};
+ return FixupConstant(Fixups, 128, 1);
+ }
case X86::VMOVAPDZ256rm:
case X86::VMOVAPSZ256rm:
case X86::VMOVUPDZ256rm:
- case X86::VMOVUPSZ256rm:
- return FixupConstant(
- {{X86::VBROADCASTSSZ256rm, 1, 32, rebuildSplatCst},
- {X86::VBROADCASTSDZ256rm, 1, 64, rebuildSplatCst},
- {X86::VBROADCASTF32X4Z256rm, 1, 128, rebuildSplatCst}},
- 256, 1);
+ case X86::VMOVUPSZ256rm: {
+ FixupEntry Fixups[] = {
+ {X86::VBROADCASTSSZ256rm, 1, 32, rebuildSplatCst},
+ {MultiDomain ? X86::VPMOVSXBQZ256rm : 0, 4, 8, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXBQZ256rm : 0, 4, 8, rebuildZExtCst},
+ {X86::VBROADCASTSDZ256rm, 1, 64, rebuildSplatCst},
+ {MultiDomain ? X86::VPMOVSXBDZ256rm : 0, 8, 8, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXBDZ256rm : 0, 8, 8, rebuildZExtCst},
+ {MultiDomain ? X86::VPMOVSXWQZ256rm : 0, 4, 16, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXWQZ256rm : 0, 4, 16, rebuildZExtCst},
+ {X86::VBROADCASTF32X4Z256rm, 1, 128, rebuildSplatCst},
+ {MultiDomain ? X86::VPMOVSXWDZ256rm : 0, 8, 16, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXWDZ256rm : 0, 8, 16, rebuildZExtCst},
+ {MultiDomain ? X86::VPMOVSXDQZ256rm : 0, 4, 32, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXDQZ256rm : 0, 4, 32, rebuildZExtCst}};
+ return FixupConstant(Fixups, 256, 1);
+ }
case X86::VMOVAPDZrm:
case X86::VMOVAPSZrm:
case X86::VMOVUPDZrm:
- case X86::VMOVUPSZrm:
- return FixupConstant({{X86::VBROADCASTSSZrm, 1, 32, rebuildSplatCst},
- {X86::VBROADCASTSDZrm, 1, 64, rebuildSplatCst},
- {X86::VBROADCASTF32X4Zrm, 1, 128, rebuildSplatCst},
- {X86::VBROADCASTF64X4Zrm, 1, 256, rebuildSplatCst}},
- 512, 1);
+ case X86::VMOVUPSZrm: {
+ FixupEntry Fixups[] = {
+ {X86::VBROADCASTSSZrm, 1, 32, rebuildSplatCst},
+ {X86::VBROADCASTSDZrm, 1, 64, rebuildSplatCst},
+ {MultiDomain ? X86::VPMOVSXBQZrm : 0, 8, 8, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXBQZrm : 0, 8, 8, rebuildZExtCst},
+ {X86::VBROADCASTF32X4Zrm, 1, 128, rebuildSplatCst},
+ {MultiDomain ? X86::VPMOVSXBDZrm : 0, 16, 8, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXBDZrm : 0, 16, 8, rebuildZExtCst},
+ {MultiDomain ? X86::VPMOVSXWQZrm : 0, 8, 16, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXWQZrm : 0, 8, 16, rebuildZExtCst},
+ {X86::VBROADCASTF64X4Zrm, 1, 256, rebuildSplatCst},
+ {MultiDomain ? X86::VPMOVSXWDZrm : 0, 16, 16, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXWDZrm : 0, 16, 16, rebuildZExtCst},
+ {MultiDomain ? X86::VPMOVSXDQZrm : 0, 8, 32, rebuildSExtCst},
+ {MultiDomain ? X86::VPMOVZXDQZrm : 0, 8, 32, rebuildZExtCst}};
+ return FixupConstant(Fixups, 512, 1);
+ }
/* Integer Loads */
case X86::MOVDQArm:
case X86::MOVDQUrm: {
diff --git a/llvm/test/CodeGen/X86/avx512-build-vector.ll b/llvm/test/CodeGen/X86/avx512-build-vector.ll
index 55478a2e93154b..b21a0c4e36c2bd 100644
--- a/llvm/test/CodeGen/X86/avx512-build-vector.ll
+++ b/llvm/test/CodeGen/X86/avx512-build-vector.ll
@@ -15,7 +15,7 @@ define <16 x float> @test3(<4 x float> %a) {
; CHECK-LABEL: test3:
; CHECK: ## %bb.0:
; CHECK-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [0,1,2,3,4,18,16,7,8,9,10,11,12,13,14,15]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [0,1,2,3,4,18,16,7,8,9,10,11,12,13,14,15]
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1
; CHECK-NEXT: vmovaps %zmm1, %zmm0
diff --git a/llvm/test/CodeGen/X86/avx512-mask-op.ll b/llvm/test/CodeGen/X86/avx512-mask-op.ll
index 8d98290ba29a6a..8aa898f3ec5765 100644
--- a/llvm/test/CodeGen/X86/avx512-mask-op.ll
+++ b/llvm/test/CodeGen/X86/avx512-mask-op.ll
@@ -1060,12 +1060,12 @@ define i32 @test13_crash(i32 %x, i32 %y) {
define <4 x i1> @test14() {
; CHECK-LABEL: test14:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [1,1,0,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm0 = [1,1,0,1]
; CHECK-NEXT: retq
;
; X86-LABEL: test14:
; X86: ## %bb.0:
-; X86-NEXT: vmovaps {{.*#+}} xmm0 = [1,1,0,1]
+; X86-NEXT: vpmovsxbd {{.*#+}} xmm0 = [1,1,0,1]
; X86-NEXT: retl
%a = bitcast i16 21845 to <16 x i1>
%b = extractelement <16 x i1> %a, i32 2
diff --git a/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll b/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
index 5078130f180779..5d901a8a380a9c 100644
--- a/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
+++ b/llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
@@ -903,7 +903,7 @@ define <8 x i16> @test_16xi16_to_8xi16_E84C94EF(<16 x i16> %vec) {
define <4 x i32> @test_8xi32_to_4xi32_perm_mask0(<8 x i32> %vec) {
; CHECK-LABEL: test_8xi32_to_4xi32_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,3,2]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [4,0,3,2]
; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT: vzeroupper
@@ -1001,7 +1001,7 @@ define <4 x i32> @test_masked_z_8xi32_to_4xi32_perm_mask2(<8 x i32> %vec, <4 x i
define <4 x i32> @test_8xi32_to_4xi32_perm_mask3(<8 x i32> %vec) {
; CHECK-LABEL: test_8xi32_to_4xi32_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [5,3,2,5]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [5,3,2,5]
; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT: vzeroupper
@@ -1189,7 +1189,7 @@ define <4 x i32> @test_masked_z_8xi32_to_4xi32_perm_mem_mask3(ptr %vp, <4 x i32>
define <8 x i32> @test_16xi32_to_8xi32_perm_mask0(<16 x i32> %vec) {
; CHECK-LABEL: test_16xi32_to_8xi32_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [1,13,11,14,7,10,1,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [1,13,11,14,7,10,1,6]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-NEXT: retq
@@ -1283,7 +1283,7 @@ define <8 x i32> @test_masked_z_16xi32_to_8xi32_perm_mask2(<16 x i32> %vec, <8 x
define <8 x i32> @test_16xi32_to_8xi32_perm_mask3(<16 x i32> %vec) {
; CHECK-LABEL: test_16xi32_to_8xi32_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [14,5,7,7,10,3,9,3]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [14,5,7,7,10,3,9,3]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-NEXT: retq
@@ -1321,7 +1321,7 @@ define <8 x i32> @test_masked_z_16xi32_to_8xi32_perm_mask3(<16 x i32> %vec, <8 x
define <4 x i32> @test_16xi32_to_4xi32_perm_mask0(<16 x i32> %vec) {
; CHECK-LABEL: test_16xi32_to_4xi32_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,12,4,6,4,12]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,12,4,6,4,12]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; CHECK-NEXT: vzeroupper
@@ -1424,7 +1424,7 @@ define <4 x i32> @test_masked_z_16xi32_to_4xi32_perm_mask2(<16 x i32> %vec, <4 x
define <4 x i32> @test_16xi32_to_4xi32_perm_mask3(<16 x i32> %vec) {
; CHECK-LABEL: test_16xi32_to_4xi32_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [3,0,0,13]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [3,0,0,13]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; CHECK-NEXT: vzeroupper
@@ -1465,7 +1465,7 @@ define <4 x i32> @test_masked_z_16xi32_to_4xi32_perm_mask3(<16 x i32> %vec, <4 x
define <8 x i32> @test_16xi32_to_8xi32_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_16xi32_to_8xi32_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [7,0,6,0,1,2,4,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm0 = [7,0,6,0,1,2,4,4]
; CHECK-NEXT: vpermps 32(%rdi), %ymm0, %ymm0
; CHECK-NEXT: retq
%vec = load <16 x i32>, ptr %vp
@@ -1768,7 +1768,7 @@ define <4 x i32> @test_masked_z_16xi32_to_4xi32_perm_mem_mask3(ptr %vp, <4 x i32
define <4 x i32> @test_16xi32_to_4xi32_perm_mask9(<16 x i32> %vec) {
; CHECK-FAST-LABEL: test_16xi32_to_4xi32_perm_mask9:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovaps {{.*#+}} xmm1 = [12,9,4,10]
+; CHECK-FAST-NEXT: vpmovsxbd {{.*#+}} xmm1 = [12,9,4,10]
; CHECK-FAST-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-FAST-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; CHECK-FAST-NEXT: vzeroupper
@@ -2050,7 +2050,7 @@ define <4 x i64> @test_masked_z_8xi64_to_4xi64_perm_mask2(<8 x i64> %vec, <4 x i
define <4 x i64> @test_8xi64_to_4xi64_perm_mask3(<8 x i64> %vec) {
; CHECK-FAST-LABEL: test_8xi64_to_4xi64_perm_mask3:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovaps {{.*#+}} ymm1 = [6,0,0,7]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm1 = [6,0,0,7]
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; CHECK-FAST-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-FAST-NEXT: retq
@@ -2185,7 +2185,7 @@ define <4 x i64> @test_masked_z_8xi64_to_4xi64_perm_mask5(<8 x i64> %vec, <4 x i
define <4 x i64> @test_8xi64_to_4xi64_perm_mask6(<8 x i64> %vec) {
; CHECK-FAST-LABEL: test_8xi64_to_4xi64_perm_mask6:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovaps {{.*#+}} ymm1 = [7,6,5,3]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm1 = [7,6,5,3]
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; CHECK-FAST-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-FAST-NEXT: retq
@@ -2711,7 +2711,7 @@ define <4 x i64> @test_masked_z_8xi64_to_4xi64_perm_mem_mask7(ptr %vp, <4 x i64>
define <2 x i64> @test_8xi64_to_2xi64_perm_mem_mask0(ptr %vp) {
; CHECK-FAST-LABEL: test_8xi64_to_2xi64_perm_mem_mask0:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovaps {{.*#+}} xmm0 = [4,1]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} xmm0 = [4,1]
; CHECK-FAST-NEXT: vpermpd (%rdi), %zmm0, %zmm0
; CHECK-FAST-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; CHECK-FAST-NEXT: vzeroupper
@@ -2847,7 +2847,7 @@ define <4 x float> @test_masked_8xfloat_to_4xfloat_perm_mask1(<8 x float> %vec,
; CHECK-LABEL: test_masked_8xfloat_to_4xfloat_perm_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
-; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [1,3,5,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm3 = [1,3,5,0]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %xmm4, %xmm2, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm3, %ymm1 {%k1}
@@ -2863,7 +2863,7 @@ define <4 x float> @test_masked_8xfloat_to_4xfloat_perm_mask1(<8 x float> %vec,
define <4 x float> @test_masked_z_8xfloat_to_4xfloat_perm_mask1(<8 x float> %vec, <4 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_to_4xfloat_perm_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm2 = [1,3,5,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm2 = [1,3,5,0]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm1, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm2, %ymm0 {%k1} {z}
@@ -2879,7 +2879,7 @@ define <4 x float> @test_masked_8xfloat_to_4xfloat_perm_mask2(<8 x float> %vec,
; CHECK-LABEL: test_masked_8xfloat_to_4xfloat_perm_mask2:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
-; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [3,2,7,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm3 = [3,2,7,0]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %xmm4, %xmm2, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm3, %ymm1 {%k1}
@@ -2895,7 +2895,7 @@ define <4 x float> @test_masked_8xfloat_to_4xfloat_perm_mask2(<8 x float> %vec,
define <4 x float> @test_masked_z_8xfloat_to_4xfloat_perm_mask2(<8 x float> %vec, <4 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_to_4xfloat_perm_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm2 = [3,2,7,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm2 = [3,2,7,0]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm1, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm2, %ymm0 {%k1} {z}
@@ -2910,7 +2910,7 @@ define <4 x float> @test_masked_z_8xfloat_to_4xfloat_perm_mask2(<8 x float> %vec
define <4 x float> @test_8xfloat_to_4xfloat_perm_mask3(<8 x float> %vec) {
; CHECK-LABEL: test_8xfloat_to_4xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [3,3,5,2]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [3,3,5,2]
; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT: vzeroupper
@@ -2922,7 +2922,7 @@ define <4 x float> @test_masked_8xfloat_to_4xfloat_perm_mask3(<8 x float> %vec,
; CHECK-LABEL: test_masked_8xfloat_to_4xfloat_perm_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
-; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [3,3,5,2]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm3 = [3,3,5,2]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %xmm4, %xmm2, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm3, %ymm1 {%k1}
@@ -2938,7 +2938,7 @@ define <4 x float> @test_masked_8xfloat_to_4xfloat_perm_mask3(<8 x float> %vec,
define <4 x float> @test_masked_z_8xfloat_to_4xfloat_perm_mask3(<8 x float> %vec, <4 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_to_4xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm2 = [3,3,5,2]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm2 = [3,3,5,2]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm1, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm2, %ymm0 {%k1} {z}
@@ -2954,7 +2954,7 @@ define <4 x float> @test_8xfloat_to_4xfloat_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_8xfloat_to_4xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 16(%rdi), %xmm1
-; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [2,6,0,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm0 = [2,6,0,1]
; CHECK-NEXT: vpermi2ps (%rdi), %xmm1, %xmm0
; CHECK-NEXT: retq
%vec = load <8 x float>, ptr %vp
@@ -2965,7 +2965,7 @@ define <4 x float> @test_masked_8xfloat_to_4xfloat_perm_mem_mask0(ptr %vp, <4 x
; CHECK-LABEL: test_masked_8xfloat_to_4xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 16(%rdi), %xmm2
-; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [2,6,0,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm3 = [2,6,0,1]
; CHECK-NEXT: vpermi2ps (%rdi), %xmm2, %xmm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %xmm2, %xmm1, %k1
@@ -2982,7 +2982,7 @@ define <4 x float> @test_masked_z_8xfloat_to_4xfloat_perm_mem_mask0(ptr %vp, <4
; CHECK-LABEL: test_masked_z_8xfloat_to_4xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 16(%rdi), %xmm2
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [2,6,0,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [2,6,0,1]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm0, %k1
; CHECK-NEXT: vpermi2ps (%rdi), %xmm2, %xmm1 {%k1} {z}
@@ -2999,7 +2999,7 @@ define <4 x float> @test_masked_8xfloat_to_4xfloat_perm_mem_mask1(ptr %vp, <4 x
; CHECK-LABEL: test_masked_8xfloat_to_4xfloat_perm_mem_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 16(%rdi), %xmm2
-; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [2,7,7,2]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm3 = [2,7,7,2]
; CHECK-NEXT: vpermi2ps (%rdi), %xmm2, %xmm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %xmm2, %xmm1, %k1
@@ -3016,7 +3016,7 @@ define <4 x float> @test_masked_z_8xfloat_to_4xfloat_perm_mem_mask1(ptr %vp, <4
; CHECK-LABEL: test_masked_z_8xfloat_to_4xfloat_perm_mem_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 16(%rdi), %xmm2
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [2,7,7,2]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [2,7,7,2]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm0, %k1
; CHECK-NEXT: vpermi2ps (%rdi), %xmm2, %xmm1 {%k1} {z}
@@ -3033,7 +3033,7 @@ define <4 x float> @test_masked_8xfloat_to_4xfloat_perm_mem_mask2(ptr %vp, <4 x
; CHECK-LABEL: test_masked_8xfloat_to_4xfloat_perm_mem_mask2:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %xmm2
-; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [3,1,3,7]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm3 = [3,1,3,7]
; CHECK-NEXT: vpermi2ps 16(%rdi), %xmm2, %xmm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %xmm2, %xmm1, %k1
@@ -3050,7 +3050,7 @@ define <4 x float> @test_masked_z_8xfloat_to_4xfloat_perm_mem_mask2(ptr %vp, <4
; CHECK-LABEL: test_masked_z_8xfloat_to_4xfloat_perm_mem_mask2:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %xmm2
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [3,1,3,7]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [3,1,3,7]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm0, %k1
; CHECK-NEXT: vpermi2ps 16(%rdi), %xmm2, %xmm1 {%k1} {z}
@@ -3067,7 +3067,7 @@ define <4 x float> @test_8xfloat_to_4xfloat_perm_mem_mask3(ptr %vp) {
; CHECK-LABEL: test_8xfloat_to_4xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %xmm1
-; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [1,3,5,3]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm0 = [1,3,5,3]
; CHECK-NEXT: vpermi2ps 16(%rdi), %xmm1, %xmm0
; CHECK-NEXT: retq
%vec = load <8 x float>, ptr %vp
@@ -3078,7 +3078,7 @@ define <4 x float> @test_masked_8xfloat_to_4xfloat_perm_mem_mask3(ptr %vp, <4 x
; CHECK-LABEL: test_masked_8xfloat_to_4xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %xmm2
-; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [1,3,5,3]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm3 = [1,3,5,3]
; CHECK-NEXT: vpermi2ps 16(%rdi), %xmm2, %xmm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %xmm2, %xmm1, %k1
@@ -3095,7 +3095,7 @@ define <4 x float> @test_masked_z_8xfloat_to_4xfloat_perm_mem_mask3(ptr %vp, <4
; CHECK-LABEL: test_masked_z_8xfloat_to_4xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %xmm2
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [1,3,5,3]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [1,3,5,3]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm0, %k1
; CHECK-NEXT: vpermi2ps 16(%rdi), %xmm2, %xmm1 {%k1} {z}
@@ -3111,7 +3111,7 @@ define <4 x float> @test_masked_z_8xfloat_to_4xfloat_perm_mem_mask3(ptr %vp, <4
define <8 x float> @test_16xfloat_to_8xfloat_perm_mask0(<16 x float> %vec) {
; CHECK-LABEL: test_16xfloat_to_8xfloat_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [0,4,12,10,8,2,11,7]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,4,12,10,8,2,11,7]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-NEXT: retq
@@ -3122,7 +3122,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mask0(<16 x float> %vec
; CHECK-LABEL: test_masked_16xfloat_to_8xfloat_perm_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [0,4,12,10,8,2,11,7]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [0,4,12,10,8,2,11,7]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -3137,7 +3137,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mask0(<16 x float> %vec
define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mask0(<16 x float> %vec, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_to_8xfloat_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [0,4,12,10,8,2,11,7]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,4,12,10,8,2,11,7]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -3152,7 +3152,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mask1(<16 x float> %vec
; CHECK-LABEL: test_masked_16xfloat_to_8xfloat_perm_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [10,12,3,12,4,15,1,14]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [10,12,3,12,4,15,1,14]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -3167,7 +3167,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mask1(<16 x float> %vec
define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mask1(<16 x float> %vec, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_to_8xfloat_perm_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [10,12,3,12,4,15,1,14]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [10,12,3,12,4,15,1,14]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -3182,7 +3182,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mask2(<16 x float> %vec
; CHECK-LABEL: test_masked_16xfloat_to_8xfloat_perm_mask2:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [0,4,8,9,6,1,4,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [0,4,8,9,6,1,4,4]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -3197,7 +3197,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mask2(<16 x float> %vec
define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mask2(<16 x float> %vec, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_to_8xfloat_perm_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [0,4,8,9,6,1,4,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,4,8,9,6,1,4,4]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -3211,7 +3211,7 @@ define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mask2(<16 x float> %v
define <8 x float> @test_16xfloat_to_8xfloat_perm_mask3(<16 x float> %vec) {
; CHECK-LABEL: test_16xfloat_to_8xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [12,14,9,0,12,4,5,8]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [12,14,9,0,12,4,5,8]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-NEXT: retq
@@ -3222,7 +3222,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mask3(<16 x float> %vec
; CHECK-LABEL: test_masked_16xfloat_to_8xfloat_perm_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [12,14,9,0,12,4,5,8]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [12,14,9,0,12,4,5,8]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -3237,7 +3237,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mask3(<16 x float> %vec
define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mask3(<16 x float> %vec, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_to_8xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [12,14,9,0,12,4,5,8]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [12,14,9,0,12,4,5,8]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -3251,7 +3251,7 @@ define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mask3(<16 x float> %v
define <4 x float> @test_16xfloat_to_4xfloat_perm_mask0(<16 x float> %vec) {
; CHECK-LABEL: test_16xfloat_to_4xfloat_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [4,8,9,10]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [4,8,9,10]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; CHECK-NEXT: vzeroupper
@@ -3263,7 +3263,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mask0(<16 x float> %vec
; CHECK-LABEL: test_masked_16xfloat_to_4xfloat_perm_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
-; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [4,8,9,10]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm3 = [4,8,9,10]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %xmm4, %xmm2, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -3279,7 +3279,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mask0(<16 x float> %vec
define <4 x float> @test_masked_z_16xfloat_to_4xfloat_perm_mask0(<16 x float> %vec, <4 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_to_4xfloat_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm2 = [4,8,9,10]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm2 = [4,8,9,10]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm1, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -3295,7 +3295,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mask1(<16 x float> %vec
; CHECK-FAST-LABEL: test_masked_16xfloat_to_4xfloat_perm_mask1:
; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
-; CHECK-FAST-NEXT: vmovaps {{.*#+}} xmm3 = [8,6,10,6]
+; CHECK-FAST-NEXT: vpmovsxbd {{.*#+}} xmm3 = [8,6,10,6]
; CHECK-FAST-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-FAST-NEXT: vcmpeqps %xmm4, %xmm2, %k1
; CHECK-FAST-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -3307,7 +3307,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mask1(<16 x float> %vec
; CHECK-FAST-PERLANE: # %bb.0:
; CHECK-FAST-PERLANE-NEXT: vextractf32x4 $2, %zmm0, %xmm3
; CHECK-FAST-PERLANE-NEXT: vextractf128 $1, %ymm0, %xmm0
-; CHECK-FAST-PERLANE-NEXT: vmovaps {{.*#+}} xmm4 = [0,6,2,6]
+; CHECK-FAST-PERLANE-NEXT: vpmovsxbd {{.*#+}} xmm4 = [0,6,2,6]
; CHECK-FAST-PERLANE-NEXT: vpermi2ps %xmm0, %xmm3, %xmm4
; CHECK-FAST-PERLANE-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-FAST-PERLANE-NEXT: vcmpeqps %xmm0, %xmm2, %k1
@@ -3323,7 +3323,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mask1(<16 x float> %vec
define <4 x float> @test_masked_z_16xfloat_to_4xfloat_perm_mask1(<16 x float> %vec, <4 x float> %mask) {
; CHECK-FAST-LABEL: test_masked_z_16xfloat_to_4xfloat_perm_mask1:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovaps {{.*#+}} xmm2 = [8,6,10,6]
+; CHECK-FAST-NEXT: vpmovsxbd {{.*#+}} xmm2 = [8,6,10,6]
; CHECK-FAST-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-FAST-NEXT: vcmpeqps %xmm3, %xmm1, %k1
; CHECK-FAST-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -3335,7 +3335,7 @@ define <4 x float> @test_masked_z_16xfloat_to_4xfloat_perm_mask1(<16 x float> %v
; CHECK-FAST-PERLANE: # %bb.0:
; CHECK-FAST-PERLANE-NEXT: vextractf32x4 $2, %zmm0, %xmm2
; CHECK-FAST-PERLANE-NEXT: vextractf128 $1, %ymm0, %xmm3
-; CHECK-FAST-PERLANE-NEXT: vmovaps {{.*#+}} xmm0 = [0,6,2,6]
+; CHECK-FAST-PERLANE-NEXT: vpmovsxbd {{.*#+}} xmm0 = [0,6,2,6]
; CHECK-FAST-PERLANE-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-FAST-PERLANE-NEXT: vcmpeqps %xmm4, %xmm1, %k1
; CHECK-FAST-PERLANE-NEXT: vpermi2ps %xmm3, %xmm2, %xmm0 {%k1} {z}
@@ -3381,7 +3381,7 @@ define <4 x float> @test_masked_z_16xfloat_to_4xfloat_perm_mask2(<16 x float> %v
define <4 x float> @test_16xfloat_to_4xfloat_perm_mask3(<16 x float> %vec) {
; CHECK-LABEL: test_16xfloat_to_4xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [10,2,11,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [10,2,11,6]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; CHECK-NEXT: vzeroupper
@@ -3393,7 +3393,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mask3(<16 x float> %vec
; CHECK-LABEL: test_masked_16xfloat_to_4xfloat_perm_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
-; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [10,2,11,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm3 = [10,2,11,6]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %xmm4, %xmm2, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -3409,7 +3409,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mask3(<16 x float> %vec
define <4 x float> @test_masked_z_16xfloat_to_4xfloat_perm_mask3(<16 x float> %vec, <4 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_to_4xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm2 = [10,2,11,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm2 = [10,2,11,6]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm1, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -3425,7 +3425,7 @@ define <8 x float> @test_16xfloat_to_8xfloat_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_16xfloat_to_8xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %ymm1
-; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [7,6,7,11,5,10,0,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm0 = [7,6,7,11,5,10,0,4]
; CHECK-NEXT: vpermi2ps 32(%rdi), %ymm1, %ymm0
; CHECK-NEXT: retq
%vec = load <16 x float>, ptr %vp
@@ -3436,7 +3436,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mem_mask0(ptr %vp, <8 x
; CHECK-LABEL: test_masked_16xfloat_to_8xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %ymm2
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [7,6,7,11,5,10,0,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [7,6,7,11,5,10,0,4]
; CHECK-NEXT: vpermi2ps 32(%rdi), %ymm2, %ymm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %ymm2, %ymm1, %k1
@@ -3453,7 +3453,7 @@ define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mem_mask0(ptr %vp, <8
; CHECK-LABEL: test_masked_z_16xfloat_to_8xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %ymm2
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [7,6,7,11,5,10,0,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [7,6,7,11,5,10,0,4]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm0, %k1
; CHECK-NEXT: vpermi2ps 32(%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -3470,7 +3470,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mem_mask1(ptr %vp, <8 x
; CHECK-LABEL: test_masked_16xfloat_to_8xfloat_perm_mem_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %ymm2
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [11,0,9,0,7,14,0,8]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [11,0,9,0,7,14,0,8]
; CHECK-NEXT: vpermi2ps 32(%rdi), %ymm2, %ymm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %ymm2, %ymm1, %k1
@@ -3487,7 +3487,7 @@ define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mem_mask1(ptr %vp, <8
; CHECK-LABEL: test_masked_z_16xfloat_to_8xfloat_perm_mem_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %ymm2
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [11,0,9,0,7,14,0,8]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [11,0,9,0,7,14,0,8]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm0, %k1
; CHECK-NEXT: vpermi2ps 32(%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -3504,7 +3504,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mem_mask2(ptr %vp, <8 x
; CHECK-FAST-LABEL: test_masked_16xfloat_to_8xfloat_perm_mem_mask2:
; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: vmovaps 32(%rdi), %ymm2
-; CHECK-FAST-NEXT: vmovaps {{.*#+}} ymm3 = [9,5,2,3,2,8,8,1]
+; CHECK-FAST-NEXT: vpmovsxbd {{.*#+}} ymm3 = [9,5,2,3,2,8,8,1]
; CHECK-FAST-NEXT: vpermi2ps (%rdi), %ymm2, %ymm3
; CHECK-FAST-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-FAST-NEXT: vcmpeqps %ymm2, %ymm1, %k1
@@ -3514,7 +3514,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mem_mask2(ptr %vp, <8 x
; CHECK-FAST-PERLANE-LABEL: test_masked_16xfloat_to_8xfloat_perm_mem_mask2:
; CHECK-FAST-PERLANE: # %bb.0:
; CHECK-FAST-PERLANE-NEXT: vmovaps (%rdi), %xmm2
-; CHECK-FAST-PERLANE-NEXT: vmovaps {{.*#+}} ymm3 = [1,13,10,11,10,0,0,9]
+; CHECK-FAST-PERLANE-NEXT: vpmovsxbd {{.*#+}} ymm3 = [1,13,10,11,10,0,0,9]
; CHECK-FAST-PERLANE-NEXT: vpermi2ps 32(%rdi), %ymm2, %ymm3
; CHECK-FAST-PERLANE-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-FAST-PERLANE-NEXT: vcmpeqps %ymm2, %ymm1, %k1
@@ -3531,7 +3531,7 @@ define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mem_mask2(ptr %vp, <8
; CHECK-FAST-LABEL: test_masked_z_16xfloat_to_8xfloat_perm_mem_mask2:
; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: vmovaps 32(%rdi), %ymm2
-; CHECK-FAST-NEXT: vmovaps {{.*#+}} ymm1 = [9,5,2,3,2,8,8,1]
+; CHECK-FAST-NEXT: vpmovsxbd {{.*#+}} ymm1 = [9,5,2,3,2,8,8,1]
; CHECK-FAST-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-FAST-NEXT: vcmpeqps %ymm3, %ymm0, %k1
; CHECK-FAST-NEXT: vpermi2ps (%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -3541,7 +3541,7 @@ define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mem_mask2(ptr %vp, <8
; CHECK-FAST-PERLANE-LABEL: test_masked_z_16xfloat_to_8xfloat_perm_mem_mask2:
; CHECK-FAST-PERLANE: # %bb.0:
; CHECK-FAST-PERLANE-NEXT: vmovaps (%rdi), %xmm2
-; CHECK-FAST-PERLANE-NEXT: vmovaps {{.*#+}} ymm1 = [1,13,10,11,10,0,0,9]
+; CHECK-FAST-PERLANE-NEXT: vpmovsxbd {{.*#+}} ymm1 = [1,13,10,11,10,0,0,9]
; CHECK-FAST-PERLANE-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-FAST-PERLANE-NEXT: vcmpeqps %ymm3, %ymm0, %k1
; CHECK-FAST-PERLANE-NEXT: vpermi2ps 32(%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -3558,7 +3558,7 @@ define <8 x float> @test_16xfloat_to_8xfloat_perm_mem_mask3(ptr %vp) {
; CHECK-LABEL: test_16xfloat_to_8xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 32(%rdi), %ymm1
-; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [7,5,3,3,11,4,12,9]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm0 = [7,5,3,3,11,4,12,9]
; CHECK-NEXT: vpermi2ps (%rdi), %ymm1, %ymm0
; CHECK-NEXT: retq
%vec = load <16 x float>, ptr %vp
@@ -3569,7 +3569,7 @@ define <8 x float> @test_masked_16xfloat_to_8xfloat_perm_mem_mask3(ptr %vp, <8 x
; CHECK-LABEL: test_masked_16xfloat_to_8xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 32(%rdi), %ymm2
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [7,5,3,3,11,4,12,9]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [7,5,3,3,11,4,12,9]
; CHECK-NEXT: vpermi2ps (%rdi), %ymm2, %ymm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %ymm2, %ymm1, %k1
@@ -3586,7 +3586,7 @@ define <8 x float> @test_masked_z_16xfloat_to_8xfloat_perm_mem_mask3(ptr %vp, <8
; CHECK-LABEL: test_masked_z_16xfloat_to_8xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 32(%rdi), %ymm2
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [7,5,3,3,11,4,12,9]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [7,5,3,3,11,4,12,9]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm0, %k1
; CHECK-NEXT: vpermi2ps (%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -3603,7 +3603,7 @@ define <4 x float> @test_16xfloat_to_4xfloat_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_16xfloat_to_4xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermpd $231, 32(%rdi), %ymm1 # ymm1 = mem[3,1,2,3]
-; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,6,7,3]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm0 = [0,6,7,3]
; CHECK-NEXT: vpermi2ps 16(%rdi), %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -3615,7 +3615,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mem_mask0(ptr %vp, <4 x
; CHECK-LABEL: test_masked_16xfloat_to_4xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermpd $231, 32(%rdi), %ymm2 # ymm2 = mem[3,1,2,3]
-; CHECK-NEXT: vmovaps {{.*#+}} xmm3 = [0,6,7,3]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm3 = [0,6,7,3]
; CHECK-NEXT: vpermi2ps 16(%rdi), %xmm2, %xmm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %xmm2, %xmm1, %k1
@@ -3633,7 +3633,7 @@ define <4 x float> @test_masked_z_16xfloat_to_4xfloat_perm_mem_mask0(ptr %vp, <4
; CHECK-LABEL: test_masked_z_16xfloat_to_4xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermpd $231, 32(%rdi), %ymm2 # ymm2 = mem[3,1,2,3]
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [0,6,7,3]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,6,7,3]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm0, %k1
; CHECK-NEXT: vpermi2ps 16(%rdi), %xmm2, %xmm1 {%k1} {z}
@@ -3651,8 +3651,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mem_mask1(ptr %vp, <4 x
; CHECK-LABEL: test_masked_16xfloat_to_4xfloat_perm_mem_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 32(%rdi), %ymm2
-; CHECK-NEXT: vbroadcastf128 {{.*#+}} ymm3 = [0,10,6,15,0,10,6,15]
-; CHECK-NEXT: # ymm3 = mem[0,1,0,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [0,10,6,15,0,0,0,0]
; CHECK-NEXT: vpermi2ps (%rdi), %ymm2, %ymm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %xmm2, %xmm1, %k1
@@ -3670,8 +3669,7 @@ define <4 x float> @test_masked_z_16xfloat_to_4xfloat_perm_mem_mask1(ptr %vp, <4
; CHECK-LABEL: test_masked_z_16xfloat_to_4xfloat_perm_mem_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps 32(%rdi), %ymm2
-; CHECK-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,10,6,15,0,10,6,15]
-; CHECK-NEXT: # ymm1 = mem[0,1,0,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,10,6,15,0,0,0,0]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm0, %k1
; CHECK-NEXT: vpermi2ps (%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -3726,7 +3724,7 @@ define <4 x float> @test_masked_z_16xfloat_to_4xfloat_perm_mem_mask2(ptr %vp, <4
define <4 x float> @test_16xfloat_to_4xfloat_perm_mem_mask3(ptr %vp) {
; CHECK-LABEL: test_16xfloat_to_4xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [3,3,15,9]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [3,3,15,9]
; CHECK-NEXT: vmovaps (%rdi), %ymm0
; CHECK-NEXT: vpermt2ps 32(%rdi), %ymm1, %ymm0
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
@@ -3739,7 +3737,7 @@ define <4 x float> @test_16xfloat_to_4xfloat_perm_mem_mask3(ptr %vp) {
define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mem_mask3(ptr %vp, <4 x float> %vec2, <4 x float> %mask) {
; CHECK-LABEL: test_masked_16xfloat_to_4xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm2 = [3,3,15,9]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm2 = [3,3,15,9]
; CHECK-NEXT: vmovaps (%rdi), %ymm3
; CHECK-NEXT: vpermt2ps 32(%rdi), %ymm2, %ymm3
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
@@ -3757,7 +3755,7 @@ define <4 x float> @test_masked_16xfloat_to_4xfloat_perm_mem_mask3(ptr %vp, <4 x
define <4 x float> @test_masked_z_16xfloat_to_4xfloat_perm_mem_mask3(ptr %vp, <4 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_to_4xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} xmm2 = [3,3,15,9]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm2 = [3,3,15,9]
; CHECK-NEXT: vmovaps (%rdi), %ymm1
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %xmm3, %xmm0, %k1
@@ -3917,8 +3915,7 @@ define <2 x double> @test_masked_z_4xdouble_to_2xdouble_perm_mem_mask1(ptr %vp,
define <4 x double> @test_8xdouble_to_4xdouble_perm_mask0(<8 x double> %vec) {
; CHECK-LABEL: test_8xdouble_to_4xdouble_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [7,3,7,3]
-; CHECK-NEXT: # ymm1 = mem[0,1,0,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm1 = [7,3,7,3]
; CHECK-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-NEXT: retq
@@ -3929,8 +3926,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask0(<8 x double> %v
; CHECK-LABEL: test_masked_8xdouble_to_4xdouble_perm_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
-; CHECK-NEXT: vbroadcastf128 {{.*#+}} ymm3 = [7,3,7,3]
-; CHECK-NEXT: # ymm3 = mem[0,1,0,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm3 = [7,3,7,3]
; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqpd %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -3945,8 +3941,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask0(<8 x double> %v
define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask0(<8 x double> %vec, <4 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [7,3,7,3]
-; CHECK-NEXT: # ymm2 = mem[0,1,0,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm2 = [7,3,7,3]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -3961,7 +3956,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask1(<8 x double> %v
; CHECK-LABEL: test_masked_8xdouble_to_4xdouble_perm_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
-; CHECK-NEXT: vmovapd {{.*#+}} ymm3 = [2,0,7,6]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm3 = [2,0,7,6]
; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqpd %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -3976,7 +3971,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask1(<8 x double> %v
define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask1(<8 x double> %vec, <4 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} ymm2 = [2,0,7,6]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm2 = [2,0,7,6]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -4016,7 +4011,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask2(<8 x double>
define <4 x double> @test_8xdouble_to_4xdouble_perm_mask3(<8 x double> %vec) {
; CHECK-LABEL: test_8xdouble_to_4xdouble_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,1,4]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,2,1,4]
; CHECK-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-NEXT: retq
@@ -4027,7 +4022,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask3(<8 x double> %v
; CHECK-LABEL: test_masked_8xdouble_to_4xdouble_perm_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
-; CHECK-NEXT: vmovapd {{.*#+}} ymm3 = [0,2,1,4]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm3 = [0,2,1,4]
; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqpd %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -4042,7 +4037,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask3(<8 x double> %v
define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask3(<8 x double> %vec, <4 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} ymm2 = [0,2,1,4]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm2 = [0,2,1,4]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -4056,7 +4051,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask3(<8 x double>
define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask4(<8 x double> %vec, <4 x double> %vec2, <4 x double> %mask) {
; CHECK-FAST-LABEL: test_masked_8xdouble_to_4xdouble_perm_mask4:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} xmm3 = [1,5]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} xmm3 = [1,5]
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm3, %zmm0
; CHECK-FAST-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-FAST-NEXT: vcmpeqpd %ymm3, %ymm2, %k1
@@ -4082,7 +4077,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask4(<8 x double> %v
define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask4(<8 x double> %vec, <4 x double> %mask) {
; CHECK-FAST-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask4:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} xmm2 = [1,5]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} xmm2 = [1,5]
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm2, %zmm0
; CHECK-FAST-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-FAST-NEXT: vcmpeqpd %ymm2, %ymm1, %k1
@@ -4106,7 +4101,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask5(<8 x double> %v
; CHECK-LABEL: test_masked_8xdouble_to_4xdouble_perm_mask5:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
-; CHECK-NEXT: vmovapd {{.*#+}} ymm3 = [2,6,2,2]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm3 = [2,6,2,2]
; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqpd %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -4121,7 +4116,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask5(<8 x double> %v
define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask5(<8 x double> %vec, <4 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask5:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} ymm2 = [2,6,2,2]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm2 = [2,6,2,2]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -4135,7 +4130,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask5(<8 x double>
define <4 x double> @test_8xdouble_to_4xdouble_perm_mask6(<8 x double> %vec) {
; CHECK-FAST-LABEL: test_8xdouble_to_4xdouble_perm_mask6:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovaps {{.*#+}} ymm1 = [5,0,7,0]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm1 = [5,0,7,0]
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; CHECK-FAST-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-FAST-NEXT: retq
@@ -4153,7 +4148,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask6(<8 x double> %v
; CHECK-FAST-LABEL: test_masked_8xdouble_to_4xdouble_perm_mask6:
; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} ymm3 = [5,0,7,0]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm3 = [5,0,7,0]
; CHECK-FAST-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-FAST-NEXT: vcmpeqpd %ymm4, %ymm2, %k1
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -4178,7 +4173,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask6(<8 x double> %v
define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask6(<8 x double> %vec, <4 x double> %mask) {
; CHECK-FAST-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask6:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} ymm2 = [5,0,7,0]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm2 = [5,0,7,0]
; CHECK-FAST-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-FAST-NEXT: vcmpeqpd %ymm3, %ymm1, %k1
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -4202,7 +4197,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask7(<8 x double> %v
; CHECK-FAST-LABEL: test_masked_8xdouble_to_4xdouble_perm_mask7:
; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} ymm3 = [3,5,0,6]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm3 = [3,5,0,6]
; CHECK-FAST-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-FAST-NEXT: vcmpeqpd %ymm4, %ymm2, %k1
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -4227,7 +4222,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mask7(<8 x double> %v
define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask7(<8 x double> %vec, <4 x double> %mask) {
; CHECK-FAST-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask7:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} ymm2 = [3,5,0,6]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm2 = [3,5,0,6]
; CHECK-FAST-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-FAST-NEXT: vcmpeqpd %ymm3, %ymm1, %k1
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -4250,7 +4245,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask7(<8 x double>
define <2 x double> @test_8xdouble_to_2xdouble_perm_mask0(<8 x double> %vec) {
; CHECK-FAST-LABEL: test_8xdouble_to_2xdouble_perm_mask0:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,0,0,0,0,0,0,6,0,0,0,0,0,0,0]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} xmm1 = [0,6]
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; CHECK-FAST-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; CHECK-FAST-NEXT: vzeroupper
@@ -4269,7 +4264,7 @@ define <2 x double> @test_masked_8xdouble_to_2xdouble_perm_mask0(<8 x double> %v
; CHECK-FAST-LABEL: test_masked_8xdouble_to_2xdouble_perm_mask0:
; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} xmm3 = [0,0,0,0,0,0,0,0,6,0,0,0,0,0,0,0]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} xmm3 = [0,6]
; CHECK-FAST-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-FAST-NEXT: vcmpeqpd %xmm4, %xmm2, %k1
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -4295,7 +4290,7 @@ define <2 x double> @test_masked_8xdouble_to_2xdouble_perm_mask0(<8 x double> %v
define <2 x double> @test_masked_z_8xdouble_to_2xdouble_perm_mask0(<8 x double> %vec, <2 x double> %mask) {
; CHECK-FAST-LABEL: test_masked_z_8xdouble_to_2xdouble_perm_mask0:
; CHECK-FAST: # %bb.0:
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} xmm2 = [0,0,0,0,0,0,0,0,6,0,0,0,0,0,0,0]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} xmm2 = [0,6]
; CHECK-FAST-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-FAST-NEXT: vcmpeqpd %xmm3, %xmm1, %k1
; CHECK-FAST-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -4320,7 +4315,7 @@ define <2 x double> @test_masked_8xdouble_to_2xdouble_perm_mask1(<8 x double> %v
; CHECK-LABEL: test_masked_8xdouble_to_2xdouble_perm_mask1:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
-; CHECK-NEXT: vmovapd {{.*#+}} xmm3 = [3,7]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} xmm3 = [3,7]
; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqpd %xmm4, %xmm2, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -4336,7 +4331,7 @@ define <2 x double> @test_masked_8xdouble_to_2xdouble_perm_mask1(<8 x double> %v
define <2 x double> @test_masked_z_8xdouble_to_2xdouble_perm_mask1(<8 x double> %vec, <2 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_to_2xdouble_perm_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} xmm2 = [3,7]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} xmm2 = [3,7]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %xmm3, %xmm1, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -4352,7 +4347,7 @@ define <4 x double> @test_8xdouble_to_4xdouble_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_8xdouble_to_4xdouble_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %ymm1
-; CHECK-NEXT: vmovapd {{.*#+}} ymm0 = [1,6,7,2]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm0 = [1,6,7,2]
; CHECK-NEXT: vpermi2pd 32(%rdi), %ymm1, %ymm0
; CHECK-NEXT: retq
%vec = load <8 x double>, ptr %vp
@@ -4363,7 +4358,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mem_mask0(ptr %vp, <4
; CHECK-LABEL: test_masked_8xdouble_to_4xdouble_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %ymm2
-; CHECK-NEXT: vmovapd {{.*#+}} ymm3 = [1,6,7,2]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm3 = [1,6,7,2]
; CHECK-NEXT: vpermi2pd 32(%rdi), %ymm2, %ymm3
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %ymm2, %ymm1, %k1
@@ -4380,7 +4375,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mem_mask0(ptr %vp,
; CHECK-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mem_mask0:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %ymm2
-; CHECK-NEXT: vmovapd {{.*#+}} ymm1 = [1,6,7,2]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm1 = [1,6,7,2]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %ymm3, %ymm0, %k1
; CHECK-NEXT: vpermi2pd 32(%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -4397,7 +4392,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mem_mask1(ptr %vp, <4
; CHECK-FAST-LABEL: test_masked_8xdouble_to_4xdouble_perm_mem_mask1:
; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: vbroadcastsd 32(%rdi), %ymm2
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} ymm3 = [7,0,6,2]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm3 = [7,0,6,2]
; CHECK-FAST-NEXT: vpermi2pd (%rdi), %ymm2, %ymm3
; CHECK-FAST-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-FAST-NEXT: vcmpeqpd %ymm2, %ymm1, %k1
@@ -4422,7 +4417,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mem_mask1(ptr %vp,
; CHECK-FAST-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mem_mask1:
; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: vbroadcastsd 32(%rdi), %ymm2
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} ymm1 = [7,0,6,2]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm1 = [7,0,6,2]
; CHECK-FAST-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-FAST-NEXT: vcmpeqpd %ymm3, %ymm0, %k1
; CHECK-FAST-NEXT: vpermi2pd (%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -4447,7 +4442,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mem_mask2(ptr %vp, <4
; CHECK-FAST-LABEL: test_masked_8xdouble_to_4xdouble_perm_mem_mask2:
; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: vmovapd (%rdi), %ymm2
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} ymm3 = [1,2,3,4]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm3 = [1,2,3,4]
; CHECK-FAST-NEXT: vpermi2pd 32(%rdi), %ymm2, %ymm3
; CHECK-FAST-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-FAST-NEXT: vcmpeqpd %ymm2, %ymm1, %k1
@@ -4473,7 +4468,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mem_mask2(ptr %vp,
; CHECK-FAST-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mem_mask2:
; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: vmovapd (%rdi), %ymm2
-; CHECK-FAST-NEXT: vmovapd {{.*#+}} ymm1 = [1,2,3,4]
+; CHECK-FAST-NEXT: vpmovsxbq {{.*#+}} ymm1 = [1,2,3,4]
; CHECK-FAST-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-FAST-NEXT: vcmpeqpd %ymm3, %ymm0, %k1
; CHECK-FAST-NEXT: vpermi2pd 32(%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -4499,7 +4494,7 @@ define <4 x double> @test_8xdouble_to_4xdouble_perm_mem_mask3(ptr %vp) {
; CHECK-LABEL: test_8xdouble_to_4xdouble_perm_mem_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %ymm1
-; CHECK-NEXT: vmovapd {{.*#+}} ymm0 = [4,2,1,0]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm0 = [4,2,1,0]
; CHECK-NEXT: vpermi2pd 32(%rdi), %ymm1, %ymm0
; CHECK-NEXT: retq
%vec = load <8 x double>, ptr %vp
@@ -4510,7 +4505,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mem_mask3(ptr %vp, <4
; CHECK-LABEL: test_masked_8xdouble_to_4xdouble_perm_mem_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %ymm2
-; CHECK-NEXT: vmovapd {{.*#+}} ymm3 = [4,2,1,0]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm3 = [4,2,1,0]
; CHECK-NEXT: vpermi2pd 32(%rdi), %ymm2, %ymm3
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %ymm2, %ymm1, %k1
@@ -4527,7 +4522,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mem_mask3(ptr %vp,
; CHECK-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mem_mask3:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd (%rdi), %ymm2
-; CHECK-NEXT: vmovapd {{.*#+}} ymm1 = [4,2,1,0]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm1 = [4,2,1,0]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %ymm3, %ymm0, %k1
; CHECK-NEXT: vpermi2pd 32(%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -4544,7 +4539,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mem_mask4(ptr %vp, <4
; CHECK-LABEL: test_masked_8xdouble_to_4xdouble_perm_mem_mask4:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd 32(%rdi), %ymm2
-; CHECK-NEXT: vmovapd {{.*#+}} ymm3 = [2,4,1,5]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm3 = [2,4,1,5]
; CHECK-NEXT: vpermi2pd (%rdi), %ymm2, %ymm3
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %ymm2, %ymm1, %k1
@@ -4561,7 +4556,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mem_mask4(ptr %vp,
; CHECK-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mem_mask4:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd 32(%rdi), %ymm2
-; CHECK-NEXT: vmovapd {{.*#+}} ymm1 = [2,4,1,5]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm1 = [2,4,1,5]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %ymm3, %ymm0, %k1
; CHECK-NEXT: vpermi2pd (%rdi), %ymm2, %ymm1 {%k1} {z}
@@ -4610,7 +4605,7 @@ define <4 x double> @test_8xdouble_to_4xdouble_perm_mem_mask6(ptr %vp) {
; CHECK-LABEL: test_8xdouble_to_4xdouble_perm_mem_mask6:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd 32(%rdi), %ymm1
-; CHECK-NEXT: vmovapd {{.*#+}} ymm0 = [0,2,4,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm0 = [0,2,4,1]
; CHECK-NEXT: vpermi2pd (%rdi), %ymm1, %ymm0
; CHECK-NEXT: retq
%vec = load <8 x double>, ptr %vp
@@ -4621,7 +4616,7 @@ define <4 x double> @test_masked_8xdouble_to_4xdouble_perm_mem_mask6(ptr %vp, <4
; CHECK-LABEL: test_masked_8xdouble_to_4xdouble_perm_mem_mask6:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd 32(%rdi), %ymm2
-; CHECK-NEXT: vmovapd {{.*#+}} ymm3 = [0,2,4,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm3 = [0,2,4,1]
; CHECK-NEXT: vpermi2pd (%rdi), %ymm2, %ymm3
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %ymm2, %ymm1, %k1
@@ -4638,7 +4633,7 @@ define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mem_mask6(ptr %vp,
; CHECK-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mem_mask6:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovapd 32(%rdi), %ymm2
-; CHECK-NEXT: vmovapd {{.*#+}} ymm1 = [0,2,4,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,2,4,1]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %ymm3, %ymm0, %k1
; CHECK-NEXT: vpermi2pd (%rdi), %ymm2, %ymm1 {%k1} {z}
diff --git a/llvm/test/CodeGen/X86/avx512-shuffles/permute.ll b/llvm/test/CodeGen/X86/avx512-shuffles/permute.ll
index 2103ab87a17ada..367e28eb7364e3 100644
--- a/llvm/test/CodeGen/X86/avx512-shuffles/permute.ll
+++ b/llvm/test/CodeGen/X86/avx512-shuffles/permute.ll
@@ -512,7 +512,7 @@ define <32 x i16> @test_masked_z_32xi16_perm_mem_mask3(ptr %vp, <32 x i16> %mask
define <8 x i32> @test_8xi32_perm_mask0(<8 x i32> %vec) {
; CHECK-LABEL: test_8xi32_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [4,2,0,6,7,2,3,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [4,2,0,6,7,2,3,6]
; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq
%res = shufflevector <8 x i32> %vec, <8 x i32> undef, <8 x i32> <i32 4, i32 2, i32 0, i32 6, i32 7, i32 2, i32 3, i32 6>
@@ -599,7 +599,7 @@ define <8 x i32> @test_masked_z_8xi32_perm_mask2(<8 x i32> %vec, <8 x i32> %mask
define <8 x i32> @test_8xi32_perm_mask3(<8 x i32> %vec) {
; CHECK-LABEL: test_8xi32_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [3,0,3,1,0,4,5,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [3,0,3,1,0,4,5,0]
; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq
%res = shufflevector <8 x i32> %vec, <8 x i32> undef, <8 x i32> <i32 3, i32 0, i32 3, i32 1, i32 0, i32 4, i32 5, i32 0>
@@ -634,7 +634,7 @@ define <8 x i32> @test_masked_z_8xi32_perm_mask3(<8 x i32> %vec, <8 x i32> %mask
define <8 x i32> @test_8xi32_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_8xi32_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [3,7,4,3,5,2,0,5]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm0 = [3,7,4,3,5,2,0,5]
; CHECK-NEXT: vpermps (%rdi), %ymm0, %ymm0
; CHECK-NEXT: retq
%vec = load <8 x i32>, ptr %vp
@@ -728,7 +728,7 @@ define <8 x i32> @test_masked_z_8xi32_perm_mem_mask2(ptr %vp, <8 x i32> %mask) {
define <8 x i32> @test_8xi32_perm_mem_mask3(ptr %vp) {
; CHECK-LABEL: test_8xi32_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [6,0,0,7,3,7,7,5]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm0 = [6,0,0,7,3,7,7,5]
; CHECK-NEXT: vpermps (%rdi), %ymm0, %ymm0
; CHECK-NEXT: retq
%vec = load <8 x i32>, ptr %vp
@@ -766,7 +766,7 @@ define <8 x i32> @test_masked_z_8xi32_perm_mem_mask3(ptr %vp, <8 x i32> %mask) {
define <16 x i32> @test_16xi32_perm_mask0(<16 x i32> %vec) {
; CHECK-LABEL: test_16xi32_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [14,12,11,6,4,1,6,9,14,14,6,1,12,11,0,7]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm1 = [14,12,11,6,4,1,6,9,14,14,6,1,12,11,0,7]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = shufflevector <16 x i32> %vec, <16 x i32> undef, <16 x i32> <i32 14, i32 12, i32 11, i32 6, i32 4, i32 1, i32 6, i32 9, i32 14, i32 14, i32 6, i32 1, i32 12, i32 11, i32 0, i32 7>
@@ -853,7 +853,7 @@ define <16 x i32> @test_masked_z_16xi32_perm_mask2(<16 x i32> %vec, <16 x i32> %
define <16 x i32> @test_16xi32_perm_mask3(<16 x i32> %vec) {
; CHECK-LABEL: test_16xi32_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [7,4,14,15,10,2,15,1,9,2,14,15,12,5,3,12]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm1 = [7,4,14,15,10,2,15,1,9,2,14,15,12,5,3,12]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = shufflevector <16 x i32> %vec, <16 x i32> undef, <16 x i32> <i32 7, i32 4, i32 14, i32 15, i32 10, i32 2, i32 15, i32 1, i32 9, i32 2, i32 14, i32 15, i32 12, i32 5, i32 3, i32 12>
@@ -888,7 +888,7 @@ define <16 x i32> @test_masked_z_16xi32_perm_mask3(<16 x i32> %vec, <16 x i32> %
define <16 x i32> @test_16xi32_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_16xi32_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm0 = [0,1,1,6,8,11,2,6,10,1,7,5,15,0,6,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm0 = [0,1,1,6,8,11,2,6,10,1,7,5,15,0,6,6]
; CHECK-NEXT: vpermps (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
%vec = load <16 x i32>, ptr %vp
@@ -982,7 +982,7 @@ define <16 x i32> @test_masked_z_16xi32_perm_mem_mask2(ptr %vp, <16 x i32> %mask
define <16 x i32> @test_16xi32_perm_mem_mask3(ptr %vp) {
; CHECK-LABEL: test_16xi32_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm0 = [11,7,10,12,3,12,4,15,1,14,0,4,8,9,6,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm0 = [11,7,10,12,3,12,4,15,1,14,0,4,8,9,6,1]
; CHECK-NEXT: vpermps (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
%vec = load <16 x i32>, ptr %vp
@@ -1254,7 +1254,7 @@ define <4 x i64> @test_masked_z_4xi64_perm_mem_mask3(ptr %vp, <4 x i64> %mask) {
define <8 x i64> @test_8xi64_perm_mask0(<8 x i64> %vec) {
; CHECK-LABEL: test_8xi64_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,7,6,5,5,1,6]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,4,7,6,5,5,1,6]
; CHECK-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = shufflevector <8 x i64> %vec, <8 x i64> undef, <8 x i32> <i32 0, i32 4, i32 7, i32 6, i32 5, i32 5, i32 1, i32 6>
@@ -1421,7 +1421,7 @@ define <8 x i64> @test_masked_z_8xi64_perm_imm_mask5(<8 x i64> %vec, <8 x i64> %
define <8 x i64> @test_8xi64_perm_mask6(<8 x i64> %vec) {
; CHECK-LABEL: test_8xi64_perm_mask6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [5,1,4,4,5,4,2,7]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm1 = [5,1,4,4,5,4,2,7]
; CHECK-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = shufflevector <8 x i64> %vec, <8 x i64> undef, <8 x i32> <i32 5, i32 1, i32 4, i32 4, i32 5, i32 4, i32 2, i32 7>
@@ -1480,7 +1480,7 @@ define <8 x i64> @test_masked_z_8xi64_perm_imm_mask7(<8 x i64> %vec, <8 x i64> %
define <8 x i64> @test_8xi64_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_8xi64_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm0 = [5,1,6,5,7,3,7,3]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm0 = [5,1,6,5,7,3,7,3]
; CHECK-NEXT: vpermpd (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
%vec = load <8 x i64>, ptr %vp
@@ -1661,7 +1661,7 @@ define <8 x i64> @test_masked_z_8xi64_perm_imm_mem_mask5(ptr %vp, <8 x i64> %mas
define <8 x i64> @test_8xi64_perm_mem_mask6(ptr %vp) {
; CHECK-LABEL: test_8xi64_perm_mem_mask6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm0 = [0,6,3,7,3,0,3,6]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm0 = [0,6,3,7,3,0,3,6]
; CHECK-NEXT: vpermpd (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
%vec = load <8 x i64>, ptr %vp
@@ -1725,7 +1725,7 @@ define <8 x i64> @test_masked_z_8xi64_perm_imm_mem_mask7(ptr %vp, <8 x i64> %mas
define <8 x float> @test_8xfloat_perm_mask0(<8 x float> %vec) {
; CHECK-LABEL: test_8xfloat_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [3,4,2,4,1,2,3,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [3,4,2,4,1,2,3,4]
; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq
%res = shufflevector <8 x float> %vec, <8 x float> undef, <8 x i32> <i32 3, i32 4, i32 2, i32 4, i32 1, i32 2, i32 3, i32 4>
@@ -1734,7 +1734,7 @@ define <8 x float> @test_8xfloat_perm_mask0(<8 x float> %vec) {
define <8 x float> @test_masked_8xfloat_perm_mask0(<8 x float> %vec, <8 x float> %vec2, <8 x float> %mask) {
; CHECK-LABEL: test_masked_8xfloat_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [3,4,2,4,1,2,3,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [3,4,2,4,1,2,3,4]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm3, %ymm1 {%k1}
@@ -1749,7 +1749,7 @@ define <8 x float> @test_masked_8xfloat_perm_mask0(<8 x float> %vec, <8 x float>
define <8 x float> @test_masked_z_8xfloat_perm_mask0(<8 x float> %vec, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [3,4,2,4,1,2,3,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [3,4,2,4,1,2,3,4]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm2, %ymm0 {%k1} {z}
@@ -1762,7 +1762,7 @@ define <8 x float> @test_masked_z_8xfloat_perm_mask0(<8 x float> %vec, <8 x floa
define <8 x float> @test_masked_8xfloat_perm_mask1(<8 x float> %vec, <8 x float> %vec2, <8 x float> %mask) {
; CHECK-LABEL: test_masked_8xfloat_perm_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [4,2,1,0,6,0,5,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [4,2,1,0,6,0,5,1]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm3, %ymm1 {%k1}
@@ -1777,7 +1777,7 @@ define <8 x float> @test_masked_8xfloat_perm_mask1(<8 x float> %vec, <8 x float>
define <8 x float> @test_masked_z_8xfloat_perm_mask1(<8 x float> %vec, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_perm_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [4,2,1,0,6,0,5,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [4,2,1,0,6,0,5,1]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm2, %ymm0 {%k1} {z}
@@ -1790,7 +1790,7 @@ define <8 x float> @test_masked_z_8xfloat_perm_mask1(<8 x float> %vec, <8 x floa
define <8 x float> @test_masked_8xfloat_perm_mask2(<8 x float> %vec, <8 x float> %vec2, <8 x float> %mask) {
; CHECK-LABEL: test_masked_8xfloat_perm_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [2,5,5,5,4,6,0,5]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [2,5,5,5,4,6,0,5]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm3, %ymm1 {%k1}
@@ -1805,7 +1805,7 @@ define <8 x float> @test_masked_8xfloat_perm_mask2(<8 x float> %vec, <8 x float>
define <8 x float> @test_masked_z_8xfloat_perm_mask2(<8 x float> %vec, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_perm_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [2,5,5,5,4,6,0,5]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [2,5,5,5,4,6,0,5]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm2, %ymm0 {%k1} {z}
@@ -1818,7 +1818,7 @@ define <8 x float> @test_masked_z_8xfloat_perm_mask2(<8 x float> %vec, <8 x floa
define <8 x float> @test_8xfloat_perm_mask3(<8 x float> %vec) {
; CHECK-LABEL: test_8xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [0,5,2,5,5,5,1,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,5,2,5,5,5,1,6]
; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
; CHECK-NEXT: retq
%res = shufflevector <8 x float> %vec, <8 x float> undef, <8 x i32> <i32 0, i32 5, i32 2, i32 5, i32 5, i32 5, i32 1, i32 6>
@@ -1827,7 +1827,7 @@ define <8 x float> @test_8xfloat_perm_mask3(<8 x float> %vec) {
define <8 x float> @test_masked_8xfloat_perm_mask3(<8 x float> %vec, <8 x float> %vec2, <8 x float> %mask) {
; CHECK-LABEL: test_masked_8xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm3 = [0,5,2,5,5,5,1,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm3 = [0,5,2,5,5,5,1,6]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %ymm4, %ymm2, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm3, %ymm1 {%k1}
@@ -1842,7 +1842,7 @@ define <8 x float> @test_masked_8xfloat_perm_mask3(<8 x float> %vec, <8 x float>
define <8 x float> @test_masked_z_8xfloat_perm_mask3(<8 x float> %vec, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [0,5,2,5,5,5,1,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,5,2,5,5,5,1,6]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps %ymm0, %ymm2, %ymm0 {%k1} {z}
@@ -1855,7 +1855,7 @@ define <8 x float> @test_masked_z_8xfloat_perm_mask3(<8 x float> %vec, <8 x floa
define <8 x float> @test_8xfloat_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_8xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [5,2,1,6,4,2,4,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm0 = [5,2,1,6,4,2,4,0]
; CHECK-NEXT: vpermps (%rdi), %ymm0, %ymm0
; CHECK-NEXT: retq
%vec = load <8 x float>, ptr %vp
@@ -1865,7 +1865,7 @@ define <8 x float> @test_8xfloat_perm_mem_mask0(ptr %vp) {
define <8 x float> @test_masked_8xfloat_perm_mem_mask0(ptr %vp, <8 x float> %vec2, <8 x float> %mask) {
; CHECK-LABEL: test_masked_8xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [5,2,1,6,4,2,4,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [5,2,1,6,4,2,4,0]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps (%rdi), %ymm2, %ymm0 {%k1}
@@ -1880,7 +1880,7 @@ define <8 x float> @test_masked_8xfloat_perm_mem_mask0(ptr %vp, <8 x float> %vec
define <8 x float> @test_masked_z_8xfloat_perm_mem_mask0(ptr %vp, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [5,2,1,6,4,2,4,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [5,2,1,6,4,2,4,0]
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %ymm2, %ymm0, %k1
; CHECK-NEXT: vpermps (%rdi), %ymm1, %ymm0 {%k1} {z}
@@ -1895,7 +1895,7 @@ define <8 x float> @test_masked_z_8xfloat_perm_mem_mask0(ptr %vp, <8 x float> %m
define <8 x float> @test_masked_8xfloat_perm_mem_mask1(ptr %vp, <8 x float> %vec2, <8 x float> %mask) {
; CHECK-LABEL: test_masked_8xfloat_perm_mem_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [1,3,7,4,0,6,6,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [1,3,7,4,0,6,6,6]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps (%rdi), %ymm2, %ymm0 {%k1}
@@ -1910,7 +1910,7 @@ define <8 x float> @test_masked_8xfloat_perm_mem_mask1(ptr %vp, <8 x float> %vec
define <8 x float> @test_masked_z_8xfloat_perm_mem_mask1(ptr %vp, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_perm_mem_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [1,3,7,4,0,6,6,6]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [1,3,7,4,0,6,6,6]
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %ymm2, %ymm0, %k1
; CHECK-NEXT: vpermps (%rdi), %ymm1, %ymm0 {%k1} {z}
@@ -1925,7 +1925,7 @@ define <8 x float> @test_masked_z_8xfloat_perm_mem_mask1(ptr %vp, <8 x float> %m
define <8 x float> @test_masked_8xfloat_perm_mem_mask2(ptr %vp, <8 x float> %vec2, <8 x float> %mask) {
; CHECK-LABEL: test_masked_8xfloat_perm_mem_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [4,5,1,5,6,6,2,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [4,5,1,5,6,6,2,4]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps (%rdi), %ymm2, %ymm0 {%k1}
@@ -1940,7 +1940,7 @@ define <8 x float> @test_masked_8xfloat_perm_mem_mask2(ptr %vp, <8 x float> %vec
define <8 x float> @test_masked_z_8xfloat_perm_mem_mask2(ptr %vp, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_perm_mem_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [4,5,1,5,6,6,2,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [4,5,1,5,6,6,2,4]
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %ymm2, %ymm0, %k1
; CHECK-NEXT: vpermps (%rdi), %ymm1, %ymm0 {%k1} {z}
@@ -1955,7 +1955,7 @@ define <8 x float> @test_masked_z_8xfloat_perm_mem_mask2(ptr %vp, <8 x float> %m
define <8 x float> @test_8xfloat_perm_mem_mask3(ptr %vp) {
; CHECK-LABEL: test_8xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [5,7,0,6,4,2,3,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm0 = [5,7,0,6,4,2,3,0]
; CHECK-NEXT: vpermps (%rdi), %ymm0, %ymm0
; CHECK-NEXT: retq
%vec = load <8 x float>, ptr %vp
@@ -1965,7 +1965,7 @@ define <8 x float> @test_8xfloat_perm_mem_mask3(ptr %vp) {
define <8 x float> @test_masked_8xfloat_perm_mem_mask3(ptr %vp, <8 x float> %vec2, <8 x float> %mask) {
; CHECK-LABEL: test_masked_8xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm2 = [5,7,0,6,4,2,3,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm2 = [5,7,0,6,4,2,3,0]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %ymm3, %ymm1, %k1
; CHECK-NEXT: vpermps (%rdi), %ymm2, %ymm0 {%k1}
@@ -1980,7 +1980,7 @@ define <8 x float> @test_masked_8xfloat_perm_mem_mask3(ptr %vp, <8 x float> %vec
define <8 x float> @test_masked_z_8xfloat_perm_mem_mask3(ptr %vp, <8 x float> %mask) {
; CHECK-LABEL: test_masked_z_8xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [5,7,0,6,4,2,3,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm1 = [5,7,0,6,4,2,3,0]
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %ymm2, %ymm0, %k1
; CHECK-NEXT: vpermps (%rdi), %ymm1, %ymm0 {%k1} {z}
@@ -1995,7 +1995,7 @@ define <8 x float> @test_masked_z_8xfloat_perm_mem_mask3(ptr %vp, <8 x float> %m
define <16 x float> @test_16xfloat_perm_mask0(<16 x float> %vec) {
; CHECK-LABEL: test_16xfloat_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [15,7,5,13,4,9,11,13,12,6,0,0,11,15,5,7]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm1 = [15,7,5,13,4,9,11,13,12,6,0,0,11,15,5,7]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = shufflevector <16 x float> %vec, <16 x float> undef, <16 x i32> <i32 15, i32 7, i32 5, i32 13, i32 4, i32 9, i32 11, i32 13, i32 12, i32 6, i32 0, i32 0, i32 11, i32 15, i32 5, i32 7>
@@ -2004,7 +2004,7 @@ define <16 x float> @test_16xfloat_perm_mask0(<16 x float> %vec) {
define <16 x float> @test_masked_16xfloat_perm_mask0(<16 x float> %vec, <16 x float> %vec2, <16 x float> %mask) {
; CHECK-LABEL: test_masked_16xfloat_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm3 = [15,7,5,13,4,9,11,13,12,6,0,0,11,15,5,7]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm3 = [15,7,5,13,4,9,11,13,12,6,0,0,11,15,5,7]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %zmm4, %zmm2, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -2019,7 +2019,7 @@ define <16 x float> @test_masked_16xfloat_perm_mask0(<16 x float> %vec, <16 x fl
define <16 x float> @test_masked_z_16xfloat_perm_mask0(<16 x float> %vec, <16 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [15,7,5,13,4,9,11,13,12,6,0,0,11,15,5,7]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [15,7,5,13,4,9,11,13,12,6,0,0,11,15,5,7]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -2032,7 +2032,7 @@ define <16 x float> @test_masked_z_16xfloat_perm_mask0(<16 x float> %vec, <16 x
define <16 x float> @test_masked_16xfloat_perm_mask1(<16 x float> %vec, <16 x float> %vec2, <16 x float> %mask) {
; CHECK-LABEL: test_masked_16xfloat_perm_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm3 = [11,10,4,10,4,5,8,11,2,0,10,0,0,3,10,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm3 = [11,10,4,10,4,5,8,11,2,0,10,0,0,3,10,1]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %zmm4, %zmm2, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -2047,7 +2047,7 @@ define <16 x float> @test_masked_16xfloat_perm_mask1(<16 x float> %vec, <16 x fl
define <16 x float> @test_masked_z_16xfloat_perm_mask1(<16 x float> %vec, <16 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_perm_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [11,10,4,10,4,5,8,11,2,0,10,0,0,3,10,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [11,10,4,10,4,5,8,11,2,0,10,0,0,3,10,1]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -2060,7 +2060,7 @@ define <16 x float> @test_masked_z_16xfloat_perm_mask1(<16 x float> %vec, <16 x
define <16 x float> @test_masked_16xfloat_perm_mask2(<16 x float> %vec, <16 x float> %vec2, <16 x float> %mask) {
; CHECK-LABEL: test_masked_16xfloat_perm_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm3 = [0,15,6,14,3,6,5,2,5,15,11,6,6,4,8,11]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm3 = [0,15,6,14,3,6,5,2,5,15,11,6,6,4,8,11]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %zmm4, %zmm2, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -2075,7 +2075,7 @@ define <16 x float> @test_masked_16xfloat_perm_mask2(<16 x float> %vec, <16 x fl
define <16 x float> @test_masked_z_16xfloat_perm_mask2(<16 x float> %vec, <16 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_perm_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [0,15,6,14,3,6,5,2,5,15,11,6,6,4,8,11]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [0,15,6,14,3,6,5,2,5,15,11,6,6,4,8,11]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -2088,7 +2088,7 @@ define <16 x float> @test_masked_z_16xfloat_perm_mask2(<16 x float> %vec, <16 x
define <16 x float> @test_16xfloat_perm_mask3(<16 x float> %vec) {
; CHECK-LABEL: test_16xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [10,7,0,14,6,6,0,2,13,8,11,2,5,13,13,3]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm1 = [10,7,0,14,6,6,0,2,13,8,11,2,5,13,13,3]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = shufflevector <16 x float> %vec, <16 x float> undef, <16 x i32> <i32 10, i32 7, i32 0, i32 14, i32 6, i32 6, i32 0, i32 2, i32 13, i32 8, i32 11, i32 2, i32 5, i32 13, i32 13, i32 3>
@@ -2097,7 +2097,7 @@ define <16 x float> @test_16xfloat_perm_mask3(<16 x float> %vec) {
define <16 x float> @test_masked_16xfloat_perm_mask3(<16 x float> %vec, <16 x float> %vec2, <16 x float> %mask) {
; CHECK-LABEL: test_masked_16xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm3 = [10,7,0,14,6,6,0,2,13,8,11,2,5,13,13,3]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm3 = [10,7,0,14,6,6,0,2,13,8,11,2,5,13,13,3]
; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqps %zmm4, %zmm2, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm3, %zmm1 {%k1}
@@ -2112,7 +2112,7 @@ define <16 x float> @test_masked_16xfloat_perm_mask3(<16 x float> %vec, <16 x fl
define <16 x float> @test_masked_z_16xfloat_perm_mask3(<16 x float> %vec, <16 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_perm_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [10,7,0,14,6,6,0,2,13,8,11,2,5,13,13,3]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [10,7,0,14,6,6,0,2,13,8,11,2,5,13,13,3]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermps %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -2125,7 +2125,7 @@ define <16 x float> @test_masked_z_16xfloat_perm_mask3(<16 x float> %vec, <16 x
define <16 x float> @test_16xfloat_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_16xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm0 = [10,2,1,14,9,9,7,2,9,4,12,11,0,14,0,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm0 = [10,2,1,14,9,9,7,2,9,4,12,11,0,14,0,1]
; CHECK-NEXT: vpermps (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
%vec = load <16 x float>, ptr %vp
@@ -2135,7 +2135,7 @@ define <16 x float> @test_16xfloat_perm_mem_mask0(ptr %vp) {
define <16 x float> @test_masked_16xfloat_perm_mem_mask0(ptr %vp, <16 x float> %vec2, <16 x float> %mask) {
; CHECK-LABEL: test_masked_16xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [10,2,1,14,9,9,7,2,9,4,12,11,0,14,0,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [10,2,1,14,9,9,7,2,9,4,12,11,0,14,0,1]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermps (%rdi), %zmm2, %zmm0 {%k1}
@@ -2150,7 +2150,7 @@ define <16 x float> @test_masked_16xfloat_perm_mem_mask0(ptr %vp, <16 x float> %
define <16 x float> @test_masked_z_16xfloat_perm_mem_mask0(ptr %vp, <16 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [10,2,1,14,9,9,7,2,9,4,12,11,0,14,0,1]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm1 = [10,2,1,14,9,9,7,2,9,4,12,11,0,14,0,1]
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %zmm2, %zmm0, %k1
; CHECK-NEXT: vpermps (%rdi), %zmm1, %zmm0 {%k1} {z}
@@ -2165,7 +2165,7 @@ define <16 x float> @test_masked_z_16xfloat_perm_mem_mask0(ptr %vp, <16 x float>
define <16 x float> @test_masked_16xfloat_perm_mem_mask1(ptr %vp, <16 x float> %vec2, <16 x float> %mask) {
; CHECK-LABEL: test_masked_16xfloat_perm_mem_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [4,2,3,5,11,6,4,7,6,4,14,8,15,12,9,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [4,2,3,5,11,6,4,7,6,4,14,8,15,12,9,4]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermps (%rdi), %zmm2, %zmm0 {%k1}
@@ -2180,7 +2180,7 @@ define <16 x float> @test_masked_16xfloat_perm_mem_mask1(ptr %vp, <16 x float> %
define <16 x float> @test_masked_z_16xfloat_perm_mem_mask1(ptr %vp, <16 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_perm_mem_mask1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [4,2,3,5,11,6,4,7,6,4,14,8,15,12,9,4]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm1 = [4,2,3,5,11,6,4,7,6,4,14,8,15,12,9,4]
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %zmm2, %zmm0, %k1
; CHECK-NEXT: vpermps (%rdi), %zmm1, %zmm0 {%k1} {z}
@@ -2195,7 +2195,7 @@ define <16 x float> @test_masked_z_16xfloat_perm_mem_mask1(ptr %vp, <16 x float>
define <16 x float> @test_masked_16xfloat_perm_mem_mask2(ptr %vp, <16 x float> %vec2, <16 x float> %mask) {
; CHECK-LABEL: test_masked_16xfloat_perm_mem_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [10,7,11,6,7,0,11,0,10,9,12,4,10,3,8,5]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [10,7,11,6,7,0,11,0,10,9,12,4,10,3,8,5]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermps (%rdi), %zmm2, %zmm0 {%k1}
@@ -2210,7 +2210,7 @@ define <16 x float> @test_masked_16xfloat_perm_mem_mask2(ptr %vp, <16 x float> %
define <16 x float> @test_masked_z_16xfloat_perm_mem_mask2(ptr %vp, <16 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_perm_mem_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [10,7,11,6,7,0,11,0,10,9,12,4,10,3,8,5]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm1 = [10,7,11,6,7,0,11,0,10,9,12,4,10,3,8,5]
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %zmm2, %zmm0, %k1
; CHECK-NEXT: vpermps (%rdi), %zmm1, %zmm0 {%k1} {z}
@@ -2225,7 +2225,7 @@ define <16 x float> @test_masked_z_16xfloat_perm_mem_mask2(ptr %vp, <16 x float>
define <16 x float> @test_16xfloat_perm_mem_mask3(ptr %vp) {
; CHECK-LABEL: test_16xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm0 = [15,15,3,9,5,15,14,9,11,10,5,14,14,5,11,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm0 = [15,15,3,9,5,15,14,9,11,10,5,14,14,5,11,0]
; CHECK-NEXT: vpermps (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
%vec = load <16 x float>, ptr %vp
@@ -2235,7 +2235,7 @@ define <16 x float> @test_16xfloat_perm_mem_mask3(ptr %vp) {
define <16 x float> @test_masked_16xfloat_perm_mem_mask3(ptr %vp, <16 x float> %vec2, <16 x float> %mask) {
; CHECK-LABEL: test_masked_16xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [15,15,3,9,5,15,14,9,11,10,5,14,14,5,11,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [15,15,3,9,5,15,14,9,11,10,5,14,14,5,11,0]
; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqps %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermps (%rdi), %zmm2, %zmm0 {%k1}
@@ -2250,7 +2250,7 @@ define <16 x float> @test_masked_16xfloat_perm_mem_mask3(ptr %vp, <16 x float> %
define <16 x float> @test_masked_z_16xfloat_perm_mem_mask3(ptr %vp, <16 x float> %mask) {
; CHECK-LABEL: test_masked_z_16xfloat_perm_mem_mask3:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [15,15,3,9,5,15,14,9,11,10,5,14,14,5,11,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm1 = [15,15,3,9,5,15,14,9,11,10,5,14,14,5,11,0]
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqps %zmm2, %zmm0, %k1
; CHECK-NEXT: vpermps (%rdi), %zmm1, %zmm0 {%k1} {z}
@@ -2515,7 +2515,7 @@ define <4 x double> @test_masked_z_4xdouble_perm_mem_mask3(ptr %vp, <4 x double>
define <8 x double> @test_8xdouble_perm_mask0(<8 x double> %vec) {
; CHECK-LABEL: test_8xdouble_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [5,7,4,2,7,4,3,4]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm1 = [5,7,4,2,7,4,3,4]
; CHECK-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = shufflevector <8 x double> %vec, <8 x double> undef, <8 x i32> <i32 5, i32 7, i32 4, i32 2, i32 7, i32 4, i32 3, i32 4>
@@ -2524,7 +2524,7 @@ define <8 x double> @test_8xdouble_perm_mask0(<8 x double> %vec) {
define <8 x double> @test_masked_8xdouble_perm_mask0(<8 x double> %vec, <8 x double> %vec2, <8 x double> %mask) {
; CHECK-LABEL: test_masked_8xdouble_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm3 = [5,7,4,2,7,4,3,4]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm3 = [5,7,4,2,7,4,3,4]
; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqpd %zmm4, %zmm2, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -2539,7 +2539,7 @@ define <8 x double> @test_masked_8xdouble_perm_mask0(<8 x double> %vec, <8 x dou
define <8 x double> @test_masked_z_8xdouble_perm_mask0(<8 x double> %vec, <8 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_perm_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm2 = [5,7,4,2,7,4,3,4]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm2 = [5,7,4,2,7,4,3,4]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -2578,7 +2578,7 @@ define <8 x double> @test_masked_z_8xdouble_perm_imm_mask1(<8 x double> %vec, <8
define <8 x double> @test_masked_8xdouble_perm_mask2(<8 x double> %vec, <8 x double> %vec2, <8 x double> %mask) {
; CHECK-LABEL: test_masked_8xdouble_perm_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm3 = [7,5,5,5,3,5,1,7]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm3 = [7,5,5,5,3,5,1,7]
; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqpd %zmm4, %zmm2, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -2593,7 +2593,7 @@ define <8 x double> @test_masked_8xdouble_perm_mask2(<8 x double> %vec, <8 x dou
define <8 x double> @test_masked_z_8xdouble_perm_mask2(<8 x double> %vec, <8 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_perm_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm2 = [7,5,5,5,3,5,1,7]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm2 = [7,5,5,5,3,5,1,7]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -2640,7 +2640,7 @@ define <8 x double> @test_masked_z_8xdouble_perm_imm_mask3(<8 x double> %vec, <8
define <8 x double> @test_masked_8xdouble_perm_mask4(<8 x double> %vec, <8 x double> %vec2, <8 x double> %mask) {
; CHECK-LABEL: test_masked_8xdouble_perm_mask4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm3 = [3,5,3,4,6,5,7,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm3 = [3,5,3,4,6,5,7,1]
; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqpd %zmm4, %zmm2, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -2655,7 +2655,7 @@ define <8 x double> @test_masked_8xdouble_perm_mask4(<8 x double> %vec, <8 x dou
define <8 x double> @test_masked_z_8xdouble_perm_mask4(<8 x double> %vec, <8 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_perm_mask4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm2 = [3,5,3,4,6,5,7,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm2 = [3,5,3,4,6,5,7,1]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -2694,7 +2694,7 @@ define <8 x double> @test_masked_z_8xdouble_perm_imm_mask5(<8 x double> %vec, <8
define <8 x double> @test_8xdouble_perm_mask6(<8 x double> %vec) {
; CHECK-LABEL: test_8xdouble_perm_mask6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [2,7,6,4,0,0,0,2]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm1 = [2,7,6,4,0,0,0,2]
; CHECK-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
%res = shufflevector <8 x double> %vec, <8 x double> undef, <8 x i32> <i32 2, i32 7, i32 6, i32 4, i32 0, i32 0, i32 0, i32 2>
@@ -2703,7 +2703,7 @@ define <8 x double> @test_8xdouble_perm_mask6(<8 x double> %vec) {
define <8 x double> @test_masked_8xdouble_perm_mask6(<8 x double> %vec, <8 x double> %vec2, <8 x double> %mask) {
; CHECK-LABEL: test_masked_8xdouble_perm_mask6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm3 = [2,7,6,4,0,0,0,2]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm3 = [2,7,6,4,0,0,0,2]
; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vcmpeqpd %zmm4, %zmm2, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm3, %zmm1 {%k1}
@@ -2718,7 +2718,7 @@ define <8 x double> @test_masked_8xdouble_perm_mask6(<8 x double> %vec, <8 x dou
define <8 x double> @test_masked_z_8xdouble_perm_mask6(<8 x double> %vec, <8 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_perm_mask6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm2 = [2,7,6,4,0,0,0,2]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm2 = [2,7,6,4,0,0,0,2]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermpd %zmm0, %zmm2, %zmm0 {%k1} {z}
@@ -2757,7 +2757,7 @@ define <8 x double> @test_masked_z_8xdouble_perm_imm_mask7(<8 x double> %vec, <8
define <8 x double> @test_8xdouble_perm_mem_mask0(ptr %vp) {
; CHECK-LABEL: test_8xdouble_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm0 = [0,3,4,0,4,2,0,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm0 = [0,3,4,0,4,2,0,1]
; CHECK-NEXT: vpermpd (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
%vec = load <8 x double>, ptr %vp
@@ -2767,7 +2767,7 @@ define <8 x double> @test_8xdouble_perm_mem_mask0(ptr %vp) {
define <8 x double> @test_masked_8xdouble_perm_mem_mask0(ptr %vp, <8 x double> %vec2, <8 x double> %mask) {
; CHECK-LABEL: test_masked_8xdouble_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm2 = [0,3,4,0,4,2,0,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm2 = [0,3,4,0,4,2,0,1]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermpd (%rdi), %zmm2, %zmm0 {%k1}
@@ -2782,7 +2782,7 @@ define <8 x double> @test_masked_8xdouble_perm_mem_mask0(ptr %vp, <8 x double> %
define <8 x double> @test_masked_z_8xdouble_perm_mem_mask0(ptr %vp, <8 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_perm_mem_mask0:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm1 = [0,3,4,0,4,2,0,1]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,3,4,0,4,2,0,1]
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %zmm2, %zmm0, %k1
; CHECK-NEXT: vpermpd (%rdi), %zmm1, %zmm0 {%k1} {z}
@@ -2825,7 +2825,7 @@ define <8 x double> @test_masked_z_8xdouble_perm_imm_mem_mask1(ptr %vp, <8 x dou
define <8 x double> @test_masked_8xdouble_perm_mem_mask2(ptr %vp, <8 x double> %vec2, <8 x double> %mask) {
; CHECK-LABEL: test_masked_8xdouble_perm_mem_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm2 = [6,7,2,7,7,6,2,5]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm2 = [6,7,2,7,7,6,2,5]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermpd (%rdi), %zmm2, %zmm0 {%k1}
@@ -2840,7 +2840,7 @@ define <8 x double> @test_masked_8xdouble_perm_mem_mask2(ptr %vp, <8 x double> %
define <8 x double> @test_masked_z_8xdouble_perm_mem_mask2(ptr %vp, <8 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_perm_mem_mask2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm1 = [6,7,2,7,7,6,2,5]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm1 = [6,7,2,7,7,6,2,5]
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %zmm2, %zmm0, %k1
; CHECK-NEXT: vpermpd (%rdi), %zmm1, %zmm0 {%k1} {z}
@@ -2892,7 +2892,7 @@ define <8 x double> @test_masked_z_8xdouble_perm_imm_mem_mask3(ptr %vp, <8 x dou
define <8 x double> @test_masked_8xdouble_perm_mem_mask4(ptr %vp, <8 x double> %vec2, <8 x double> %mask) {
; CHECK-LABEL: test_masked_8xdouble_perm_mem_mask4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm2 = [1,1,3,5,6,0,6,0]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm2 = [1,1,3,5,6,0,6,0]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermpd (%rdi), %zmm2, %zmm0 {%k1}
@@ -2907,7 +2907,7 @@ define <8 x double> @test_masked_8xdouble_perm_mem_mask4(ptr %vp, <8 x double> %
define <8 x double> @test_masked_z_8xdouble_perm_mem_mask4(ptr %vp, <8 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_perm_mem_mask4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm1 = [1,1,3,5,6,0,6,0]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm1 = [1,1,3,5,6,0,6,0]
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %zmm2, %zmm0, %k1
; CHECK-NEXT: vpermpd (%rdi), %zmm1, %zmm0 {%k1} {z}
@@ -2950,7 +2950,7 @@ define <8 x double> @test_masked_z_8xdouble_perm_imm_mem_mask5(ptr %vp, <8 x dou
define <8 x double> @test_8xdouble_perm_mem_mask6(ptr %vp) {
; CHECK-LABEL: test_8xdouble_perm_mem_mask6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm0 = [2,4,0,4,6,1,2,5]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm0 = [2,4,0,4,6,1,2,5]
; CHECK-NEXT: vpermpd (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
%vec = load <8 x double>, ptr %vp
@@ -2960,7 +2960,7 @@ define <8 x double> @test_8xdouble_perm_mem_mask6(ptr %vp) {
define <8 x double> @test_masked_8xdouble_perm_mem_mask6(ptr %vp, <8 x double> %vec2, <8 x double> %mask) {
; CHECK-LABEL: test_masked_8xdouble_perm_mem_mask6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm2 = [2,4,0,4,6,1,2,5]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm2 = [2,4,0,4,6,1,2,5]
; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vcmpeqpd %zmm3, %zmm1, %k1
; CHECK-NEXT: vpermpd (%rdi), %zmm2, %zmm0 {%k1}
@@ -2975,7 +2975,7 @@ define <8 x double> @test_masked_8xdouble_perm_mem_mask6(ptr %vp, <8 x double> %
define <8 x double> @test_masked_z_8xdouble_perm_mem_mask6(ptr %vp, <8 x double> %mask) {
; CHECK-LABEL: test_masked_z_8xdouble_perm_mem_mask6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovapd {{.*#+}} zmm1 = [2,4,0,4,6,1,2,5]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm1 = [2,4,0,4,6,1,2,5]
; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpeqpd %zmm2, %zmm0, %k1
; CHECK-NEXT: vpermpd (%rdi), %zmm1, %zmm0 {%k1} {z}
diff --git a/llvm/test/CodeGen/X86/avx512vl-intrinsics.ll b/llvm/test/CodeGen/X86/avx512vl-intrinsics.ll
index 6de09c745b32a2..0973824fbb0efa 100644
--- a/llvm/test/CodeGen/X86/avx512vl-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512vl-intrinsics.ll
@@ -7031,18 +7031,18 @@ define <4 x double> @test_mask_vfmadd256_pd_rmkz(<4 x double> %a0, <4 x double>
define <8 x i32> @combine_vpermi2d_vpermps(<16 x i32> noundef %a) {
; X86-LABEL: combine_vpermi2d_vpermps:
; X86: # %bb.0:
-; X86-NEXT: vmovaps {{.*#+}} ymm1 = [14,13,6,3,5,15,0,1]
-; X86-NEXT: # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0x0d,A,A,A,A]
-; X86-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-NEXT: vpmovsxbd {{.*#+}} ymm1 = [14,13,6,3,5,15,0,1]
+; X86-NEXT: # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x21,0x0d,A,A,A,A]
+; X86-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpermps %zmm0, %zmm1, %zmm0 # encoding: [0x62,0xf2,0x75,0x48,0x16,0xc0]
; X86-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: combine_vpermi2d_vpermps:
; X64: # %bb.0:
-; X64-NEXT: vmovaps {{.*#+}} ymm1 = [14,13,6,3,5,15,0,1]
-; X64-NEXT: # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0x0d,A,A,A,A]
-; X64-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-NEXT: vpmovsxbd {{.*#+}} ymm1 = [14,13,6,3,5,15,0,1]
+; X64-NEXT: # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x21,0x0d,A,A,A,A]
+; X64-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpermps %zmm0, %zmm1, %zmm0 # encoding: [0x62,0xf2,0x75,0x48,0x16,0xc0]
; X64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; X64-NEXT: retq # encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/combine-or.ll b/llvm/test/CodeGen/X86/combine-or.ll
index 4060355495eb3b..d9c6d7053be746 100644
--- a/llvm/test/CodeGen/X86/combine-or.ll
+++ b/llvm/test/CodeGen/X86/combine-or.ll
@@ -29,11 +29,16 @@ define <2 x i64> @or_zext_v2i32(<2 x i32> %a0) {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295]
; SSE-NEXT: retq
;
-; AVX-LABEL: or_zext_v2i32:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovddup {{.*#+}} xmm0 = [4294967295,4294967295]
-; AVX-NEXT: # xmm0 = mem[0,0]
-; AVX-NEXT: retq
+; AVX1-LABEL: or_zext_v2i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967295,0,4294967295,0]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: or_zext_v2i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovddup {{.*#+}} xmm0 = [4294967295,4294967295]
+; AVX2-NEXT: # xmm0 = mem[0,0]
+; AVX2-NEXT: retq
%1 = zext <2 x i32> %a0 to <2 x i64>
%2 = or <2 x i64> %1, <i64 4294967295, i64 4294967295>
ret <2 x i64> %2
diff --git a/llvm/test/CodeGen/X86/combine-sub-usat.ll b/llvm/test/CodeGen/X86/combine-sub-usat.ll
index 13d5c9f1856456..b70e3fcd779c5d 100644
--- a/llvm/test/CodeGen/X86/combine-sub-usat.ll
+++ b/llvm/test/CodeGen/X86/combine-sub-usat.ll
@@ -52,10 +52,20 @@ define <8 x i16> @combine_constfold_v8i16() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,254,0,65534,0,0,0]
; SSE-NEXT: retq
;
-; AVX-LABEL: combine_constfold_v8i16:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,254,0,65534,0,0,0]
-; AVX-NEXT: retq
+; AVX1-LABEL: combine_constfold_v8i16:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,254,0,65534,0,0,0]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: combine_constfold_v8i16:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,254,0,65534,0,0,0]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: combine_constfold_v8i16:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovzxwd {{.*#+}} xmm0 = [0,254,65534,0]
+; AVX512-NEXT: retq
%res = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> <i16 0, i16 1, i16 255, i16 65535, i16 -1, i16 -255, i16 -65535, i16 1>, <8 x i16> <i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535>)
ret <8 x i16> %res
}
@@ -66,10 +76,20 @@ define <8 x i16> @combine_constfold_undef_v8i16() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,65534,0,0,0]
; SSE-NEXT: retq
;
-; AVX-LABEL: combine_constfold_undef_v8i16:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65534,0,0,0]
-; AVX-NEXT: retq
+; AVX1-LABEL: combine_constfold_undef_v8i16:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65534,0,0,0]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: combine_constfold_undef_v8i16:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65534,0,0,0]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: combine_constfold_undef_v8i16:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = [0,65534]
+; AVX512-NEXT: retq
%res = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> <i16 undef, i16 1, i16 undef, i16 65535, i16 -1, i16 -255, i16 -65535, i16 1>, <8 x i16> <i16 1, i16 undef, i16 undef, i16 65535, i16 1, i16 65535, i16 1, i16 65535>)
ret <8 x i16> %res
}
diff --git a/llvm/test/CodeGen/X86/expand-vp-cast-intrinsics.ll b/llvm/test/CodeGen/X86/expand-vp-cast-intrinsics.ll
index 0a52dfff71eda4..dea29b7b5b93df 100644
--- a/llvm/test/CodeGen/X86/expand-vp-cast-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/expand-vp-cast-intrinsics.ll
@@ -532,7 +532,7 @@ define <2 x half> @vfptrunc_v2f16_v2f64(<2 x double> %a, <2 x i1> %m, i32 zeroex
; AVX512-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
; AVX512-NEXT: callq __truncdfhf2 at PLT
; AVX512-NEXT: vpbroadcastw %xmm0, %xmm1
-; AVX512-NEXT: vmovss {{.*#+}} xmm0 = [4,0,0,0]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [4,0]
; AVX512-NEXT: vpermi2ps (%rsp), %xmm1, %xmm0 # 16-byte Folded Reload
; AVX512-NEXT: addq $40, %rsp
; AVX512-NEXT: .cfi_def_cfa_offset 8
diff --git a/llvm/test/CodeGen/X86/extract-concat.ll b/llvm/test/CodeGen/X86/extract-concat.ll
index e7415dcf229f40..f12693469a3f6e 100644
--- a/llvm/test/CodeGen/X86/extract-concat.ll
+++ b/llvm/test/CodeGen/X86/extract-concat.ll
@@ -84,9 +84,9 @@ define <16 x i64> @catcat(<4 x i64> %x) {
; AVX512F-LABEL: catcat:
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,1,1,1,1]
+; AVX512F-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,1,1,1,1]
; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm2
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [2,2,2,2,3,3,3,3]
+; AVX512F-NEXT: vpmovsxbq {{.*#+}} zmm1 = [2,2,2,2,3,3,3,3]
; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm1
; AVX512F-NEXT: vmovaps %zmm2, %zmm0
; AVX512F-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/insert-into-constant-vector.ll b/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
index 6e41e1bb87eb2f..c44945ac2d929f 100644
--- a/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
+++ b/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
@@ -436,9 +436,9 @@ define <8 x i64> @elt5_v8i64(i64 %x) {
;
; X86-AVX512F-LABEL: elt5_v8i64:
; X86-AVX512F: # %bb.0:
-; X86-AVX512F-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0]
+; X86-AVX512F-NEXT: vpmovsxbq {{.*#+}} ymm0 = [42,1,2,3]
; X86-AVX512F-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
-; X86-AVX512F-NEXT: vmovss {{.*#+}} xmm2 = [4,0,0,0]
+; X86-AVX512F-NEXT: vpmovsxbq {{.*#+}} xmm2 = [4,0]
; X86-AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; X86-AVX512F-NEXT: vinsertf128 $1, {{\.?LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
; X86-AVX512F-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
diff --git a/llvm/test/CodeGen/X86/isel-buildvector-avx.ll b/llvm/test/CodeGen/X86/isel-buildvector-avx.ll
index 91abfff2a34246..a9297f016521d4 100644
--- a/llvm/test/CodeGen/X86/isel-buildvector-avx.ll
+++ b/llvm/test/CodeGen/X86/isel-buildvector-avx.ll
@@ -43,10 +43,15 @@ define <8 x float> @test_vector_v8f32() {
}
define <4 x i64> @test_vector_v4i64() {
-; AVX-ALL-LABEL: test_vector_v4i64:
-; AVX-ALL: # %bb.0:
-; AVX-ALL-NEXT: vmovaps {{.*#+}} ymm0 = [23430,24650,1,12]
-; AVX-ALL-NEXT: retq
+; AVX-LABEL: test_vector_v4i64:
+; AVX: # %bb.0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [23430,24650,1,12]
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_vector_v4i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxwq {{.*#+}} ymm0 = [23430,24650,1,12]
+; AVX512-NEXT: retq
ret <4 x i64> <i64 23430, i64 24650, i64 1, i64 12>
}
diff --git a/llvm/test/CodeGen/X86/matrix-multiply.ll b/llvm/test/CodeGen/X86/matrix-multiply.ll
index ed668c6ef4b043..bdc1ff4c157e4f 100644
--- a/llvm/test/CodeGen/X86/matrix-multiply.ll
+++ b/llvm/test/CodeGen/X86/matrix-multiply.ll
@@ -394,7 +394,7 @@ define <9 x float> @test_mul3x3_f32(<9 x float> %a0, <9 x float> %a1) nounwind {
; AVX512F-NEXT: vaddss %xmm1, %xmm2, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512F-NEXT: vinsertf32x4 $1, %xmm7, %zmm6, %zmm2
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm0 = [0,1,2,4,5,6,16,17,18,u,u,u,u,u,u,u]
+; AVX512F-NEXT: vpmovsxbd {{.*#+}} zmm0 = [0,1,2,4,5,6,16,17,18,0,0,0,0,0,0,0]
; AVX512F-NEXT: vpermi2ps %zmm1, %zmm2, %zmm0
; AVX512F-NEXT: retq
;
@@ -453,7 +453,7 @@ define <9 x float> @test_mul3x3_f32(<9 x float> %a0, <9 x float> %a1) nounwind {
; AVX512VL-NEXT: vaddss %xmm1, %xmm2, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm5, %zmm3, %zmm2
-; AVX512VL-NEXT: vmovaps {{.*#+}} zmm0 = [0,1,2,4,5,6,16,17,18,u,u,u,u,u,u,u]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} zmm0 = [0,1,2,4,5,6,16,17,18,0,0,0,0,0,0,0]
; AVX512VL-NEXT: vpermi2ps %zmm1, %zmm2, %zmm0
; AVX512VL-NEXT: retq
entry:
@@ -762,7 +762,7 @@ define <9 x double> @test_mul3x3_f64(<9 x double> %a0, <9 x double> %a1) nounwin
; AVX512F-NEXT: vmulsd %xmm1, %xmm8, %xmm1
; AVX512F-NEXT: vaddsd %xmm1, %xmm2, %xmm1
; AVX512F-NEXT: vinsertf64x4 $1, %ymm4, %zmm3, %zmm2
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm3 = [0,1,2,4,5,6,8,9]
+; AVX512F-NEXT: vpmovsxbq {{.*#+}} zmm3 = [0,1,2,4,5,6,8,9]
; AVX512F-NEXT: vpermi2pd %zmm0, %zmm2, %zmm3
; AVX512F-NEXT: vmovsd %xmm1, 64(%rdi)
; AVX512F-NEXT: vmovapd %zmm3, (%rdi)
@@ -818,7 +818,7 @@ define <9 x double> @test_mul3x3_f64(<9 x double> %a0, <9 x double> %a1) nounwin
; AVX512VL-NEXT: vmulsd %xmm3, %xmm8, %xmm3
; AVX512VL-NEXT: vaddsd %xmm3, %xmm2, %xmm2
; AVX512VL-NEXT: vinsertf64x4 $1, %ymm4, %zmm1, %zmm1
-; AVX512VL-NEXT: vmovapd {{.*#+}} zmm3 = [0,1,2,4,5,6,8,9]
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} zmm3 = [0,1,2,4,5,6,8,9]
; AVX512VL-NEXT: vpermi2pd %zmm0, %zmm1, %zmm3
; AVX512VL-NEXT: vmovsd %xmm2, 64(%rdi)
; AVX512VL-NEXT: vmovapd %zmm3, (%rdi)
diff --git a/llvm/test/CodeGen/X86/nontemporal-4.ll b/llvm/test/CodeGen/X86/nontemporal-4.ll
index c1eff891a94874..3d86174e45103a 100644
--- a/llvm/test/CodeGen/X86/nontemporal-4.ll
+++ b/llvm/test/CodeGen/X86/nontemporal-4.ll
@@ -659,9 +659,9 @@ define void @test_constant_v4i64_align16(ptr %dst) nounwind {
;
; AVX512-LABEL: test_constant_v4i64_align16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551614,18446744073709551613]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551614,18446744073709551613]
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [0,18446744073709551615]
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
; AVX512-NEXT: retq
store <4 x i64> <i64 0, i64 -1, i64 -2, i64 -3>, ptr %dst, align 16, !nontemporal !1
@@ -687,9 +687,9 @@ define void @test_constant_v8i32_align16(ptr %dst) nounwind {
;
; AVX512-LABEL: test_constant_v8i32_align16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [4294967292,4294967291,4294967290,4294967289]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967292,4294967291,4294967290,4294967289]
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [0,4294967295,4294967294,4294967293]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [0,4294967295,4294967294,4294967293]
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
; AVX512-NEXT: retq
store <8 x i32> <i32 0, i32 -1, i32 -2, i32 -3, i32 -4, i32 -5, i32 -6, i32 -7>, ptr %dst, align 16, !nontemporal !1
@@ -1408,13 +1408,13 @@ define void @test_constant_v8i64_align16(ptr %dst) nounwind {
;
; AVX512-LABEL: test_constant_v8i64_align16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551614,18446744073709551613]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551614,18446744073709551613]
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,255,255,255,255,255,255,255,255]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [0,18446744073709551615]
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551610,18446744073709551609]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551610,18446744073709551609]
; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551612,18446744073709551611]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551612,18446744073709551611]
; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)
; AVX512-NEXT: retq
store <8 x i64> <i64 0, i64 -1, i64 -2, i64 -3, i64 -4, i64 -5, i64 -6, i64 -7>, ptr %dst, align 16, !nontemporal !1
@@ -1448,13 +1448,13 @@ define void @test_constant_v16i32_align16(ptr %dst) nounwind {
;
; AVX512-LABEL: test_constant_v16i32_align16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [4294967292,4294967291,4294967290,4294967289]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967292,4294967291,4294967290,4294967289]
; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [0,4294967295,4294967294,4294967293]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [0,4294967295,4294967294,4294967293]
; AVX512-NEXT: vmovntps %xmm0, (%rdi)
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [4294967284,4294967283,4294967282,4294967281]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967284,4294967283,4294967282,4294967281]
; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)
-; AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [4294967288,4294967287,4294967286,4294967285]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967288,4294967287,4294967286,4294967285]
; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)
; AVX512-NEXT: retq
store <16 x i32> <i32 0, i32 -1, i32 -2, i32 -3, i32 -4, i32 -5, i32 -6, i32 -7, i32 -8, i32 -9, i32 -10, i32 -11, i32 -12, i32 -13, i32 -14, i32 -15>, ptr %dst, align 16, !nontemporal !1
@@ -1634,9 +1634,9 @@ define void @test_constant_v8i64_align32(ptr %dst) nounwind {
;
; AVX512-LABEL: test_constant_v8i64_align32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551612,18446744073709551611,18446744073709551610,18446744073709551609]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [18446744073709551612,18446744073709551611,18446744073709551610,18446744073709551609]
; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)
-; AVX512-NEXT: vmovaps {{.*#+}} ymm0 = [0,18446744073709551615,18446744073709551614,18446744073709551613]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [0,18446744073709551615,18446744073709551614,18446744073709551613]
; AVX512-NEXT: vmovntps %ymm0, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
@@ -1668,9 +1668,9 @@ define void @test_constant_v16i32_align32(ptr %dst) nounwind {
;
; AVX512-LABEL: test_constant_v16i32_align32:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmovaps {{.*#+}} ymm0 = [4294967288,4294967287,4294967286,4294967285,4294967284,4294967283,4294967282,4294967281]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4294967288,4294967287,4294967286,4294967285,4294967284,4294967283,4294967282,4294967281]
; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)
-; AVX512-NEXT: vmovaps {{.*#+}} ymm0 = [0,4294967295,4294967294,4294967293,4294967292,4294967291,4294967290,4294967289]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [0,4294967295,4294967294,4294967293,4294967292,4294967291,4294967290,4294967289]
; AVX512-NEXT: vmovntps %ymm0, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr29112.ll b/llvm/test/CodeGen/X86/pr29112.ll
index b099e0c3994043..2e5c6f047292cc 100644
--- a/llvm/test/CodeGen/X86/pr29112.ll
+++ b/llvm/test/CodeGen/X86/pr29112.ll
@@ -11,29 +11,29 @@ define <4 x float> @bar(ptr %a1p, ptr %a2p, <4 x float> %a3, <4 x float> %a4, <1
; CHECK-NEXT: subq $136, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 144
; CHECK-NEXT: vmovaps %xmm1, %xmm13
-; CHECK-NEXT: vmovaps {{.*#+}} xmm5 = [3,20,1,17]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm5 = [3,20,1,17]
; CHECK-NEXT: vpermi2ps %zmm3, %zmm2, %zmm5
; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 = ymm2[0],ymm3[0],ymm2[1],ymm3[1],ymm2[4],ymm3[4],ymm2[5],ymm3[5]
; CHECK-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[2,1,2,3]
-; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [4,21,1,17,4,21,5,21]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4,21,1,17,4,21,5,21]
; CHECK-NEXT: vpermi2ps %zmm3, %zmm2, %zmm0
; CHECK-NEXT: vmovaps %zmm0, %zmm6
; CHECK-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill
-; CHECK-NEXT: vmovaps {{.*#+}} xmm4 = [4,20,1,27]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm4 = [4,20,1,27]
; CHECK-NEXT: vpermi2ps %zmm3, %zmm2, %zmm4
-; CHECK-NEXT: vmovaps {{.*#+}} ymm7 = [5,20,1,19,5,20,5,23]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm7 = [5,20,1,19,5,20,5,23]
; CHECK-NEXT: vpermi2ps %zmm3, %zmm2, %zmm7
-; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [4,20,1,19,4,20,5,23]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4,20,1,19,4,20,5,23]
; CHECK-NEXT: vpermi2ps %zmm3, %zmm2, %zmm0
-; CHECK-NEXT: vmovaps {{.*#+}} xmm12 = [4,28,1,17]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm12 = [4,28,1,17]
; CHECK-NEXT: vpermi2ps %zmm3, %zmm2, %zmm12
-; CHECK-NEXT: vmovaps {{.*#+}} ymm8 = [5,20,1,17,5,20,5,21]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm8 = [5,20,1,17,5,20,5,21]
; CHECK-NEXT: vpermi2ps %zmm3, %zmm2, %zmm8
-; CHECK-NEXT: vmovaps {{.*#+}} xmm9 = [4,30,1,22]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm9 = [4,30,1,22]
; CHECK-NEXT: vpermi2ps %zmm3, %zmm2, %zmm9
-; CHECK-NEXT: vmovaps {{.*#+}} ymm10 = [4,22,1,17,4,22,5,21]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm10 = [4,22,1,17,4,22,5,21]
; CHECK-NEXT: vpermi2ps %zmm3, %zmm2, %zmm10
-; CHECK-NEXT: vmovaps {{.*#+}} ymm11 = [4,20,3,18,4,20,7,22]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} ymm11 = [4,20,3,18,4,20,7,22]
; CHECK-NEXT: vpermi2ps %zmm3, %zmm2, %zmm11
; CHECK-NEXT: vaddps %xmm10, %xmm11, %xmm2
; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
diff --git a/llvm/test/CodeGen/X86/pr46532.ll b/llvm/test/CodeGen/X86/pr46532.ll
index cbc677229ede61..c798e74a0b231a 100644
--- a/llvm/test/CodeGen/X86/pr46532.ll
+++ b/llvm/test/CodeGen/X86/pr46532.ll
@@ -7,7 +7,7 @@ define void @WhileWithLoopInvariantOperation.21() {
; CHECK-NEXT: movq (%rax), %rax
; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovaps %xmm0, 32(%rax)
-; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = [4294967295,4294967295,0,0]
+; CHECK-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551615,0]
; CHECK-NEXT: vmaskmovps %ymm0, %ymm0, (%rax)
while.1.body.preheader:
%0 = load ptr, ptr undef, align 8, !invariant.load !0, !dereferenceable !1, !align !2
diff --git a/llvm/test/CodeGen/X86/pr78109.ll b/llvm/test/CodeGen/X86/pr78109.ll
index 26586cba37658c..78b4885319b767 100644
--- a/llvm/test/CodeGen/X86/pr78109.ll
+++ b/llvm/test/CodeGen/X86/pr78109.ll
@@ -10,15 +10,11 @@ define <4 x i32> @PR78109() {
; SSE: # %bb.0:
; SSE-NEXT: movaps {{.*#+}} xmm0 = [0,1,0,1]
; SSE-NEXT: retq
-;
-; AVX-LABEL: PR78109:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovddup {{.*#+}} xmm0 = [0,1,0,1]
-; AVX-NEXT: # xmm0 = mem[0,0]
-; AVX-NEXT: retq
%shuffle.1 = shufflevector <4 x i32> <i32 7, i32 7, i32 0, i32 7>, <4 x i32> zeroinitializer, <4 x i32> <i32 2, i32 2, i32 1, i32 1> ; <0, 0, 7, 7>
%shift = lshr <4 x i32> %shuffle.1, <i32 0, i32 0, i32 1, i32 0> ; <0, 0, 3, 7>
%shuffle.2 = shufflevector <4 x i32> %shift, <4 x i32> zeroinitializer, <4 x i32> <i32 2, i32 2, i32 0, i32 0> ; <3, 3, 0, 0>
%shuffle.3 = shufflevector <4 x i32> %shuffle.2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 2, i32 6, i32 3, i32 7> ; <0, 1, 0, 1>
ret <4 x i32> %shuffle.3
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/CodeGen/X86/pr97968.ll b/llvm/test/CodeGen/X86/pr97968.ll
index c8a0536ac43169..ca5c63cdc1c2ec 100644
--- a/llvm/test/CodeGen/X86/pr97968.ll
+++ b/llvm/test/CodeGen/X86/pr97968.ll
@@ -4,8 +4,7 @@
define <2 x i32> @PR97968(<16 x i32> %a0) {
; CHECK-LABEL: PR97968:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovddup {{.*#+}} xmm1 = [2,7,2,7]
-; CHECK-NEXT: # xmm1 = mem[0,0]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} xmm1 = [2,7,2,7]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; CHECK-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll b/llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll
index dfd17ffaed0b24..7c22330d7804b6 100644
--- a/llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll
+++ b/llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll
@@ -201,9 +201,9 @@ define <8 x i16> @test_x86_sse41_packusdw_fold() {
;
; X86-AVX512-LABEL: test_x86_sse41_packusdw_fold:
; X86-AVX512: ## %bb.0:
-; X86-AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0]
-; X86-AVX512-NEXT: ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X86-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
+; X86-AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [0,0,4294967295,0]
+; X86-AVX512-NEXT: ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x21,0x05,A,A,A,A]
+; X86-AVX512-NEXT: ## fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512-NEXT: retl ## encoding: [0xc3]
;
; X64-SSE-LABEL: test_x86_sse41_packusdw_fold:
@@ -222,9 +222,9 @@ define <8 x i16> @test_x86_sse41_packusdw_fold() {
;
; X64-AVX512-LABEL: test_x86_sse41_packusdw_fold:
; X64-AVX512: ## %bb.0:
-; X64-AVX512-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0]
-; X64-AVX512-NEXT: ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
-; X64-AVX512-NEXT: ## fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; X64-AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [0,0,4294967295,0]
+; X64-AVX512-NEXT: ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x21,0x05,A,A,A,A]
+; X64-AVX512-NEXT: ## fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> zeroinitializer, <4 x i32> <i32 65535, i32 65536, i32 -1, i32 -131072>)
ret <8 x i16> %res
diff --git a/llvm/test/CodeGen/X86/vec_fp_to_int.ll b/llvm/test/CodeGen/X86/vec_fp_to_int.ll
index a0e9f33483b69c..df2dc77dc12591 100644
--- a/llvm/test/CodeGen/X86/vec_fp_to_int.ll
+++ b/llvm/test/CodeGen/X86/vec_fp_to_int.ll
@@ -1896,10 +1896,15 @@ define <2 x i64> @fptosi_2f64_to_2i64_const() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,18446744073709551615]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptosi_2f64_to_2i64_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,18446744073709551615]
-; AVX-NEXT: retq
+; VEX-LABEL: fptosi_2f64_to_2i64_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} xmm0 = [1,18446744073709551615]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptosi_2f64_to_2i64_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [1,18446744073709551615]
+; AVX512-NEXT: retq
%cvt = fptosi <2 x double> <double 1.0, double -1.0> to <2 x i64>
ret <2 x i64> %cvt
}
@@ -1910,10 +1915,15 @@ define <4 x i32> @fptosi_2f64_to_2i32_const() {
; SSE-NEXT: movsd {{.*#+}} xmm0 = [4294967295,1,0,0]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptosi_2f64_to_2i32_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4294967295,1,0,0]
-; AVX-NEXT: retq
+; VEX-LABEL: fptosi_2f64_to_2i32_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovsd {{.*#+}} xmm0 = [4294967295,1,0,0]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptosi_2f64_to_2i32_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967295,1,0,0]
+; AVX512-NEXT: retq
%cvt = fptosi <2 x double> <double -1.0, double 1.0> to <2 x i32>
%ext = shufflevector <2 x i32> %cvt, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i32> %ext
@@ -1926,10 +1936,15 @@ define <4 x i64> @fptosi_4f64_to_4i64_const() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [2,18446744073709551613]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptosi_4f64_to_4i64_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1,18446744073709551615,2,18446744073709551613]
-; AVX-NEXT: retq
+; VEX-LABEL: fptosi_4f64_to_4i64_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} ymm0 = [1,18446744073709551615,2,18446744073709551613]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptosi_4f64_to_4i64_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [1,18446744073709551615,2,18446744073709551613]
+; AVX512-NEXT: retq
%cvt = fptosi <4 x double> <double 1.0, double -1.0, double 2.0, double -3.0> to <4 x i64>
ret <4 x i64> %cvt
}
@@ -1940,10 +1955,15 @@ define <4 x i32> @fptosi_4f64_to_4i32_const() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,1,4294967294,3]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptosi_4f64_to_4i32_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,1,4294967294,3]
-; AVX-NEXT: retq
+; VEX-LABEL: fptosi_4f64_to_4i32_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,1,4294967294,3]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptosi_4f64_to_4i32_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967295,1,4294967294,3]
+; AVX512-NEXT: retq
%cvt = fptosi <4 x double> <double -1.0, double 1.0, double -2.0, double 3.0> to <4 x i32>
ret <4 x i32> %cvt
}
@@ -1954,10 +1974,15 @@ define <2 x i64> @fptoui_2f64_to_2i64_const() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [2,4]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptoui_2f64_to_2i64_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [2,4]
-; AVX-NEXT: retq
+; VEX-LABEL: fptoui_2f64_to_2i64_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} xmm0 = [2,4]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptoui_2f64_to_2i64_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [2,4]
+; AVX512-NEXT: retq
%cvt = fptoui <2 x double> <double 2.0, double 4.0> to <2 x i64>
ret <2 x i64> %cvt
}
@@ -1968,10 +1993,15 @@ define <4 x i32> @fptoui_2f64_to_2i32_const(<2 x double> %a) {
; SSE-NEXT: movsd {{.*#+}} xmm0 = [2,4,0,0]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptoui_2f64_to_2i32_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [2,4,0,0]
-; AVX-NEXT: retq
+; VEX-LABEL: fptoui_2f64_to_2i32_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovsd {{.*#+}} xmm0 = [2,4,0,0]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptoui_2f64_to_2i32_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [2,4,0,0]
+; AVX512-NEXT: retq
%cvt = fptoui <2 x double> <double 2.0, double 4.0> to <2 x i32>
%ext = shufflevector <2 x i32> %cvt, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i32> %ext
@@ -1984,10 +2014,15 @@ define <4 x i64> @fptoui_4f64_to_4i64_const(<4 x double> %a) {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [6,8]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptoui_4f64_to_4i64_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [2,4,6,8]
-; AVX-NEXT: retq
+; VEX-LABEL: fptoui_4f64_to_4i64_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} ymm0 = [2,4,6,8]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptoui_4f64_to_4i64_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [2,4,6,8]
+; AVX512-NEXT: retq
%cvt = fptoui <4 x double> <double 2.0, double 4.0, double 6.0, double 8.0> to <4 x i64>
ret <4 x i64> %cvt
}
@@ -1998,10 +2033,15 @@ define <4 x i32> @fptoui_4f64_to_4i32_const(<4 x double> %a) {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [2,4,6,8]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptoui_4f64_to_4i32_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [2,4,6,8]
-; AVX-NEXT: retq
+; VEX-LABEL: fptoui_4f64_to_4i32_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} xmm0 = [2,4,6,8]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptoui_4f64_to_4i32_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [2,4,6,8]
+; AVX512-NEXT: retq
%cvt = fptoui <4 x double> <double 2.0, double 4.0, double 6.0, double 8.0> to <4 x i32>
ret <4 x i32> %cvt
}
@@ -2012,10 +2052,15 @@ define <4 x i32> @fptosi_4f32_to_4i32_const() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,4294967295,2,3]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptosi_4f32_to_4i32_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,4294967295,2,3]
-; AVX-NEXT: retq
+; VEX-LABEL: fptosi_4f32_to_4i32_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} xmm0 = [1,4294967295,2,3]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptosi_4f32_to_4i32_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [1,4294967295,2,3]
+; AVX512-NEXT: retq
%cvt = fptosi <4 x float> <float 1.0, float -1.0, float 2.0, float 3.0> to <4 x i32>
ret <4 x i32> %cvt
}
@@ -2027,10 +2072,15 @@ define <4 x i64> @fptosi_4f32_to_4i64_const() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [2,3]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptosi_4f32_to_4i64_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1,18446744073709551615,2,3]
-; AVX-NEXT: retq
+; VEX-LABEL: fptosi_4f32_to_4i64_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} ymm0 = [1,18446744073709551615,2,3]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptosi_4f32_to_4i64_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [1,18446744073709551615,2,3]
+; AVX512-NEXT: retq
%cvt = fptosi <4 x float> <float 1.0, float -1.0, float 2.0, float 3.0> to <4 x i64>
ret <4 x i64> %cvt
}
@@ -2042,10 +2092,15 @@ define <8 x i32> @fptosi_8f32_to_8i32_const(<8 x float> %a) {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [6,4294967288,2,4294967295]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptosi_8f32_to_8i32_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1,4294967295,2,3,6,4294967288,2,4294967295]
-; AVX-NEXT: retq
+; VEX-LABEL: fptosi_8f32_to_8i32_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} ymm0 = [1,4294967295,2,3,6,4294967288,2,4294967295]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptosi_8f32_to_8i32_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [1,4294967295,2,3,6,4294967288,2,4294967295]
+; AVX512-NEXT: retq
%cvt = fptosi <8 x float> <float 1.0, float -1.0, float 2.0, float 3.0, float 6.0, float -8.0, float 2.0, float -1.0> to <8 x i32>
ret <8 x i32> %cvt
}
@@ -2056,10 +2111,15 @@ define <4 x i32> @fptoui_4f32_to_4i32_const(<4 x float> %a) {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,2,4,6]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptoui_4f32_to_4i32_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,2,4,6]
-; AVX-NEXT: retq
+; VEX-LABEL: fptoui_4f32_to_4i32_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} xmm0 = [1,2,4,6]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptoui_4f32_to_4i32_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [1,2,4,6]
+; AVX512-NEXT: retq
%cvt = fptoui <4 x float> <float 1.0, float 2.0, float 4.0, float 6.0> to <4 x i32>
ret <4 x i32> %cvt
}
@@ -2071,10 +2131,15 @@ define <4 x i64> @fptoui_4f32_to_4i64_const() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [4,8]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptoui_4f32_to_4i64_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1,2,4,8]
-; AVX-NEXT: retq
+; VEX-LABEL: fptoui_4f32_to_4i64_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} ymm0 = [1,2,4,8]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptoui_4f32_to_4i64_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [1,2,4,8]
+; AVX512-NEXT: retq
%cvt = fptoui <4 x float> <float 1.0, float 2.0, float 4.0, float 8.0> to <4 x i64>
ret <4 x i64> %cvt
}
@@ -2086,10 +2151,15 @@ define <8 x i32> @fptoui_8f32_to_8i32_const(<8 x float> %a) {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [8,6,4,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: fptoui_8f32_to_8i32_const:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1,2,4,6,8,6,4,1]
-; AVX-NEXT: retq
+; VEX-LABEL: fptoui_8f32_to_8i32_const:
+; VEX: # %bb.0:
+; VEX-NEXT: vmovaps {{.*#+}} ymm0 = [1,2,4,6,8,6,4,1]
+; VEX-NEXT: retq
+;
+; AVX512-LABEL: fptoui_8f32_to_8i32_const:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [1,2,4,6,8,6,4,1]
+; AVX512-NEXT: retq
%cvt = fptoui <8 x float> <float 1.0, float 2.0, float 4.0, float 6.0, float 8.0, float 6.0, float 4.0, float 1.0> to <8 x i32>
ret <8 x i32> %cvt
}
diff --git a/llvm/test/CodeGen/X86/vec_minmax_sint.ll b/llvm/test/CodeGen/X86/vec_minmax_sint.ll
index ade250ac827c5c..853e29b8acfcd5 100644
--- a/llvm/test/CodeGen/X86/vec_minmax_sint.ll
+++ b/llvm/test/CodeGen/X86/vec_minmax_sint.ll
@@ -1541,10 +1541,20 @@ define <2 x i64> @max_gt_v2i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_gt_v2i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_gt_v2i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_gt_v2i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_gt_v2i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX512-NEXT: retq
%1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
%2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
%3 = icmp sgt <2 x i64> %1, %2
@@ -1559,10 +1569,20 @@ define <4 x i64> @max_gt_v4i64c() {
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX-LABEL: max_gt_v4i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_gt_v4i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_gt_v4i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_gt_v4i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
%2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
%3 = icmp sgt <4 x i64> %1, %2
@@ -1576,10 +1596,20 @@ define <4 x i32> @max_gt_v4i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_gt_v4i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_gt_v4i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_gt_v4i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_gt_v4i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp sgt <4 x i32> %1, %2
@@ -1594,10 +1624,20 @@ define <8 x i32> @max_gt_v8i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_gt_v8i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_gt_v8i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_gt_v8i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_gt_v8i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp sgt <8 x i32> %1, %2
@@ -1663,10 +1703,20 @@ define <2 x i64> @max_ge_v2i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_ge_v2i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_ge_v2i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_ge_v2i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_ge_v2i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX512-NEXT: retq
%1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
%2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
%3 = icmp sge <2 x i64> %1, %2
@@ -1681,10 +1731,20 @@ define <4 x i64> @max_ge_v4i64c() {
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX-LABEL: max_ge_v4i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_ge_v4i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_ge_v4i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_ge_v4i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
%2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
%3 = icmp sge <4 x i64> %1, %2
@@ -1698,10 +1758,20 @@ define <4 x i32> @max_ge_v4i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_ge_v4i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_ge_v4i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_ge_v4i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_ge_v4i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp sge <4 x i32> %1, %2
@@ -1716,10 +1786,20 @@ define <8 x i32> @max_ge_v8i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_ge_v8i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_ge_v8i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_ge_v8i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_ge_v8i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp sge <8 x i32> %1, %2
@@ -1785,10 +1865,20 @@ define <2 x i64> @min_lt_v2i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_lt_v2i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_lt_v2i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_lt_v2i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_lt_v2i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX512-NEXT: retq
%1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
%2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
%3 = icmp slt <2 x i64> %1, %2
@@ -1803,10 +1893,20 @@ define <4 x i64> @min_lt_v4i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_lt_v4i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_lt_v4i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_lt_v4i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_lt_v4i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
%2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
%3 = icmp slt <4 x i64> %1, %2
@@ -1820,10 +1920,20 @@ define <4 x i32> @min_lt_v4i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_lt_v4i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_lt_v4i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_lt_v4i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_lt_v4i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp slt <4 x i32> %1, %2
@@ -1838,10 +1948,20 @@ define <8 x i32> @min_lt_v8i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_lt_v8i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_lt_v8i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_lt_v8i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_lt_v8i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp slt <8 x i32> %1, %2
@@ -1907,10 +2027,20 @@ define <2 x i64> @min_le_v2i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_le_v2i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_le_v2i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_le_v2i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_le_v2i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX512-NEXT: retq
%1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
%2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
%3 = icmp sle <2 x i64> %1, %2
@@ -1925,10 +2055,20 @@ define <4 x i64> @min_le_v4i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_le_v4i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_le_v4i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_le_v4i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_le_v4i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
%2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
%3 = icmp sle <4 x i64> %1, %2
@@ -1942,10 +2082,20 @@ define <4 x i32> @min_le_v4i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_le_v4i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_le_v4i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_le_v4i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_le_v4i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp sle <4 x i32> %1, %2
@@ -1960,10 +2110,20 @@ define <8 x i32> @min_le_v8i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_le_v8i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_le_v8i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_le_v8i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_le_v8i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp sle <8 x i32> %1, %2
diff --git a/llvm/test/CodeGen/X86/vec_minmax_uint.ll b/llvm/test/CodeGen/X86/vec_minmax_uint.ll
index 3ddc882adf0aff..9b4da3f9b817f9 100644
--- a/llvm/test/CodeGen/X86/vec_minmax_uint.ll
+++ b/llvm/test/CodeGen/X86/vec_minmax_uint.ll
@@ -1653,10 +1653,20 @@ define <2 x i64> @max_gt_v2i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_gt_v2i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_gt_v2i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_gt_v2i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_gt_v2i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX512-NEXT: retq
%1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
%2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
%3 = icmp ugt <2 x i64> %1, %2
@@ -1671,10 +1681,20 @@ define <4 x i64> @max_gt_v4i64c() {
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX-LABEL: max_gt_v4i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_gt_v4i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_gt_v4i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_gt_v4i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
%2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
%3 = icmp ugt <4 x i64> %1, %2
@@ -1688,10 +1708,20 @@ define <4 x i32> @max_gt_v4i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_gt_v4i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_gt_v4i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_gt_v4i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_gt_v4i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp ugt <4 x i32> %1, %2
@@ -1706,10 +1736,20 @@ define <8 x i32> @max_gt_v8i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_gt_v8i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_gt_v8i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_gt_v8i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_gt_v8i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp ugt <8 x i32> %1, %2
@@ -1775,10 +1815,20 @@ define <2 x i64> @max_ge_v2i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_ge_v2i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_ge_v2i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_ge_v2i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_ge_v2i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551615,7]
+; AVX512-NEXT: retq
%1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
%2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
%3 = icmp uge <2 x i64> %1, %2
@@ -1793,10 +1843,20 @@ define <4 x i64> @max_ge_v4i64c() {
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX-LABEL: max_ge_v4i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_ge_v4i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_ge_v4i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_ge_v4i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
%2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
%3 = icmp uge <4 x i64> %1, %2
@@ -1810,10 +1870,20 @@ define <4 x i32> @max_ge_v4i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_ge_v4i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_ge_v4i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_ge_v4i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_ge_v4i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp uge <4 x i32> %1, %2
@@ -1828,10 +1898,20 @@ define <8 x i32> @max_ge_v8i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7]
; SSE-NEXT: retq
;
-; AVX-LABEL: max_ge_v8i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
-; AVX-NEXT: retq
+; AVX1-LABEL: max_ge_v8i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: max_ge_v8i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: max_ge_v8i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
+; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp uge <8 x i32> %1, %2
@@ -1897,10 +1977,20 @@ define <2 x i64> @min_lt_v2i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_lt_v2i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_lt_v2i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_lt_v2i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_lt_v2i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX512-NEXT: retq
%1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
%2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
%3 = icmp ult <2 x i64> %1, %2
@@ -1915,10 +2005,20 @@ define <4 x i64> @min_lt_v4i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_lt_v4i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_lt_v4i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_lt_v4i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_lt_v4i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
%2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
%3 = icmp ult <4 x i64> %1, %2
@@ -1932,10 +2032,20 @@ define <4 x i32> @min_lt_v4i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_lt_v4i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_lt_v4i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_lt_v4i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_lt_v4i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp ult <4 x i32> %1, %2
@@ -1950,10 +2060,20 @@ define <8 x i32> @min_lt_v8i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_lt_v8i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_lt_v8i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_lt_v8i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_lt_v8i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp ult <8 x i32> %1, %2
@@ -2019,10 +2139,20 @@ define <2 x i64> @min_le_v2i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_le_v2i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_le_v2i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_le_v2i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_le_v2i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [18446744073709551609,1]
+; AVX512-NEXT: retq
%1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
%2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
%3 = icmp ule <2 x i64> %1, %2
@@ -2037,10 +2167,20 @@ define <4 x i64> @min_le_v4i64c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_le_v4i64c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_le_v4i64c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_le_v4i64c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_le_v4i64c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
%2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
%3 = icmp ule <4 x i64> %1, %2
@@ -2054,10 +2194,20 @@ define <4 x i32> @min_le_v4i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_le_v4i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_le_v4i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_le_v4i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_le_v4i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
+; AVX512-NEXT: retq
%1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
%2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
%3 = icmp ule <4 x i32> %1, %2
@@ -2072,10 +2222,20 @@ define <8 x i32> @min_le_v8i32c() {
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1]
; SSE-NEXT: retq
;
-; AVX-LABEL: min_le_v8i32c:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
-; AVX-NEXT: retq
+; AVX1-LABEL: min_le_v8i32c:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: min_le_v8i32c:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: min_le_v8i32c:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
+; AVX512-NEXT: retq
%1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
%2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
%3 = icmp ule <8 x i32> %1, %2
diff --git a/llvm/test/CodeGen/X86/vector-compress.ll b/llvm/test/CodeGen/X86/vector-compress.ll
index 17b98b5ebcaeae..94a1792cb89857 100644
--- a/llvm/test/CodeGen/X86/vector-compress.ll
+++ b/llvm/test/CodeGen/X86/vector-compress.ll
@@ -903,10 +903,20 @@ define <64 x i32> @test_compress_large(<64 x i1> %mask, <64 x i32> %vec, <64 x i
}
define <4 x i32> @test_compress_all_const() {
-; CHECK-LABEL: test_compress_all_const:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = [5,9,0,0]
-; CHECK-NEXT: retq
+; AVX2-LABEL: test_compress_all_const:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovsd {{.*#+}} xmm0 = [5,9,0,0]
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: test_compress_all_const:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vpmovsxbd {{.*#+}} xmm0 = [5,9,0,0]
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: test_compress_all_const:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm0 = [5,9,0,0]
+; AVX512VL-NEXT: retq
%out = call <4 x i32> @llvm.experimental.vector.compress(<4 x i32> <i32 3, i32 5, i32 7, i32 9>,
<4 x i1> <i1 0, i1 1, i1 0, i1 1>,
<4 x i32> undef)
diff --git a/llvm/test/CodeGen/X86/vector-half-conversions.ll b/llvm/test/CodeGen/X86/vector-half-conversions.ll
index 62ee0b298ba917..54acd012d1fe47 100644
--- a/llvm/test/CodeGen/X86/vector-half-conversions.ll
+++ b/llvm/test/CodeGen/X86/vector-half-conversions.ll
@@ -3163,7 +3163,7 @@ define <2 x i16> @cvt_2f64_to_2i16(<2 x double> %a0) nounwind {
; AVX512F-NEXT: callq __truncdfhf2 at PLT
; AVX512F-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
-; AVX512F-NEXT: vmovss {{.*#+}} xmm1 = [16,0,0,0]
+; AVX512F-NEXT: vpmovsxbq {{.*#+}} xmm1 = [16,0]
; AVX512F-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload
; AVX512F-NEXT: vpermt2ps %zmm2, %zmm1, %zmm0
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
@@ -3185,7 +3185,7 @@ define <2 x i16> @cvt_2f64_to_2i16(<2 x double> %a0) nounwind {
; AVX512-FASTLANE-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
; AVX512-FASTLANE-NEXT: callq __truncdfhf2 at PLT
; AVX512-FASTLANE-NEXT: vpbroadcastw %xmm0, %xmm1
-; AVX512-FASTLANE-NEXT: vmovss {{.*#+}} xmm0 = [4,0,0,0]
+; AVX512-FASTLANE-NEXT: vpmovsxbq {{.*#+}} xmm0 = [4,0]
; AVX512-FASTLANE-NEXT: vpermi2ps (%rsp), %xmm1, %xmm0 # 16-byte Folded Reload
; AVX512-FASTLANE-NEXT: addq $40, %rsp
; AVX512-FASTLANE-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
index b7e46e51064c04..3ba41ad07ce836 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
@@ -174,11 +174,11 @@ define void @load_i32_stride6_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; AVX512-NEXT: vpinsrd $1, %r10d, %xmm4, %xmm4
; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; AVX512-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3]
-; AVX512-NEXT: vmovsd {{.*#+}} xmm2 = [4,2,0,0]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm2 = [4,2,0,0]
; AVX512-NEXT: vmovaps 32(%rdi), %ymm5
; AVX512-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0,1,2,3],mem[4,5,6,7]
; AVX512-NEXT: vpermps %ymm5, %ymm2, %ymm2
-; AVX512-NEXT: vmovsd {{.*#+}} xmm6 = [5,3,0,0]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm6 = [5,3,0,0]
; AVX512-NEXT: vpermps %ymm5, %ymm6, %ymm5
; AVX512-NEXT: vmovq %xmm3, (%rsi)
; AVX512-NEXT: vmovq %xmm1, (%rdx)
@@ -203,11 +203,11 @@ define void @load_i32_stride6_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; AVX512-FCP-NEXT: vpermi2d %xmm3, %xmm1, %xmm2
; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} xmm5 = [3,5,0,0]
; AVX512-FCP-NEXT: vpermi2d %xmm3, %xmm1, %xmm5
-; AVX512-FCP-NEXT: vmovsd {{.*#+}} xmm1 = [4,2,0,0]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} xmm1 = [4,2,0,0]
; AVX512-FCP-NEXT: vmovaps 32(%rdi), %ymm3
; AVX512-FCP-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3],mem[4,5,6,7]
; AVX512-FCP-NEXT: vpermps %ymm3, %ymm1, %ymm1
-; AVX512-FCP-NEXT: vmovsd {{.*#+}} xmm6 = [5,3,0,0]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} xmm6 = [5,3,0,0]
; AVX512-FCP-NEXT: vpermps %ymm3, %ymm6, %ymm3
; AVX512-FCP-NEXT: vmovq %xmm0, (%rsi)
; AVX512-FCP-NEXT: vmovq %xmm4, (%rdx)
@@ -234,11 +234,11 @@ define void @load_i32_stride6_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; AVX512DQ-NEXT: vpinsrd $1, %r10d, %xmm4, %xmm4
; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; AVX512DQ-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3]
-; AVX512DQ-NEXT: vmovsd {{.*#+}} xmm2 = [4,2,0,0]
+; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} xmm2 = [4,2,0,0]
; AVX512DQ-NEXT: vmovaps 32(%rdi), %ymm5
; AVX512DQ-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0,1,2,3],mem[4,5,6,7]
; AVX512DQ-NEXT: vpermps %ymm5, %ymm2, %ymm2
-; AVX512DQ-NEXT: vmovsd {{.*#+}} xmm6 = [5,3,0,0]
+; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} xmm6 = [5,3,0,0]
; AVX512DQ-NEXT: vpermps %ymm5, %ymm6, %ymm5
; AVX512DQ-NEXT: vmovq %xmm3, (%rsi)
; AVX512DQ-NEXT: vmovq %xmm1, (%rdx)
@@ -263,11 +263,11 @@ define void @load_i32_stride6_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; AVX512DQ-FCP-NEXT: vpermi2d %xmm3, %xmm1, %xmm2
; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} xmm5 = [3,5,0,0]
; AVX512DQ-FCP-NEXT: vpermi2d %xmm3, %xmm1, %xmm5
-; AVX512DQ-FCP-NEXT: vmovsd {{.*#+}} xmm1 = [4,2,0,0]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} xmm1 = [4,2,0,0]
; AVX512DQ-FCP-NEXT: vmovaps 32(%rdi), %ymm3
; AVX512DQ-FCP-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3],mem[4,5,6,7]
; AVX512DQ-FCP-NEXT: vpermps %ymm3, %ymm1, %ymm1
-; AVX512DQ-FCP-NEXT: vmovsd {{.*#+}} xmm6 = [5,3,0,0]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} xmm6 = [5,3,0,0]
; AVX512DQ-FCP-NEXT: vpermps %ymm3, %ymm6, %ymm3
; AVX512DQ-FCP-NEXT: vmovq %xmm0, (%rsi)
; AVX512DQ-FCP-NEXT: vmovq %xmm4, (%rdx)
@@ -294,11 +294,11 @@ define void @load_i32_stride6_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; AVX512BW-NEXT: vpinsrd $1, %r10d, %xmm4, %xmm4
; AVX512BW-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3]
-; AVX512BW-NEXT: vmovsd {{.*#+}} xmm2 = [4,2,0,0]
+; AVX512BW-NEXT: vpmovsxbd {{.*#+}} xmm2 = [4,2,0,0]
; AVX512BW-NEXT: vmovaps 32(%rdi), %ymm5
; AVX512BW-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0,1,2,3],mem[4,5,6,7]
; AVX512BW-NEXT: vpermps %ymm5, %ymm2, %ymm2
-; AVX512BW-NEXT: vmovsd {{.*#+}} xmm6 = [5,3,0,0]
+; AVX512BW-NEXT: vpmovsxbd {{.*#+}} xmm6 = [5,3,0,0]
; AVX512BW-NEXT: vpermps %ymm5, %ymm6, %ymm5
; AVX512BW-NEXT: vmovq %xmm3, (%rsi)
; AVX512BW-NEXT: vmovq %xmm1, (%rdx)
@@ -323,11 +323,11 @@ define void @load_i32_stride6_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; AVX512BW-FCP-NEXT: vpermi2d %xmm3, %xmm1, %xmm2
; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} xmm5 = [3,5,0,0]
; AVX512BW-FCP-NEXT: vpermi2d %xmm3, %xmm1, %xmm5
-; AVX512BW-FCP-NEXT: vmovsd {{.*#+}} xmm1 = [4,2,0,0]
+; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} xmm1 = [4,2,0,0]
; AVX512BW-FCP-NEXT: vmovaps 32(%rdi), %ymm3
; AVX512BW-FCP-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3],mem[4,5,6,7]
; AVX512BW-FCP-NEXT: vpermps %ymm3, %ymm1, %ymm1
-; AVX512BW-FCP-NEXT: vmovsd {{.*#+}} xmm6 = [5,3,0,0]
+; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} xmm6 = [5,3,0,0]
; AVX512BW-FCP-NEXT: vpermps %ymm3, %ymm6, %ymm3
; AVX512BW-FCP-NEXT: vmovq %xmm0, (%rsi)
; AVX512BW-FCP-NEXT: vmovq %xmm4, (%rdx)
@@ -354,11 +354,11 @@ define void @load_i32_stride6_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; AVX512DQ-BW-NEXT: vpinsrd $1, %r10d, %xmm4, %xmm4
; AVX512DQ-BW-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; AVX512DQ-BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3]
-; AVX512DQ-BW-NEXT: vmovsd {{.*#+}} xmm2 = [4,2,0,0]
+; AVX512DQ-BW-NEXT: vpmovsxbd {{.*#+}} xmm2 = [4,2,0,0]
; AVX512DQ-BW-NEXT: vmovaps 32(%rdi), %ymm5
; AVX512DQ-BW-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0,1,2,3],mem[4,5,6,7]
; AVX512DQ-BW-NEXT: vpermps %ymm5, %ymm2, %ymm2
-; AVX512DQ-BW-NEXT: vmovsd {{.*#+}} xmm6 = [5,3,0,0]
+; AVX512DQ-BW-NEXT: vpmovsxbd {{.*#+}} xmm6 = [5,3,0,0]
; AVX512DQ-BW-NEXT: vpermps %ymm5, %ymm6, %ymm5
; AVX512DQ-BW-NEXT: vmovq %xmm3, (%rsi)
; AVX512DQ-BW-NEXT: vmovq %xmm1, (%rdx)
@@ -383,11 +383,11 @@ define void @load_i32_stride6_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; AVX512DQ-BW-FCP-NEXT: vpermi2d %xmm3, %xmm1, %xmm2
; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} xmm5 = [3,5,0,0]
; AVX512DQ-BW-FCP-NEXT: vpermi2d %xmm3, %xmm1, %xmm5
-; AVX512DQ-BW-FCP-NEXT: vmovsd {{.*#+}} xmm1 = [4,2,0,0]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} xmm1 = [4,2,0,0]
; AVX512DQ-BW-FCP-NEXT: vmovaps 32(%rdi), %ymm3
; AVX512DQ-BW-FCP-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3],mem[4,5,6,7]
; AVX512DQ-BW-FCP-NEXT: vpermps %ymm3, %ymm1, %ymm1
-; AVX512DQ-BW-FCP-NEXT: vmovsd {{.*#+}} xmm6 = [5,3,0,0]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} xmm6 = [5,3,0,0]
; AVX512DQ-BW-FCP-NEXT: vpermps %ymm3, %ymm6, %ymm3
; AVX512DQ-BW-FCP-NEXT: vmovq %xmm0, (%rsi)
; AVX512DQ-BW-FCP-NEXT: vmovq %xmm4, (%rdx)
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
index 6f534ee9cdf0bc..93a84e30412d63 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
@@ -96,7 +96,7 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
;
; AVX512-FCP-LABEL: load_i64_stride3_vf2:
; AVX512-FCP: # %bb.0:
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} xmm0 = [1,4]
+; AVX512-FCP-NEXT: vpmovsxbq {{.*#+}} xmm0 = [1,4]
; AVX512-FCP-NEXT: vmovaps (%rdi), %zmm1
; AVX512-FCP-NEXT: vpermpd %zmm1, %zmm0, %zmm0
; AVX512-FCP-NEXT: vpermpd {{.*#+}} zmm1 = zmm1[0,3,2,3,4,7,6,7]
@@ -122,7 +122,7 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
;
; AVX512DQ-FCP-LABEL: load_i64_stride3_vf2:
; AVX512DQ-FCP: # %bb.0:
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} xmm0 = [1,4]
+; AVX512DQ-FCP-NEXT: vpmovsxbq {{.*#+}} xmm0 = [1,4]
; AVX512DQ-FCP-NEXT: vmovaps (%rdi), %zmm1
; AVX512DQ-FCP-NEXT: vpermpd %zmm1, %zmm0, %zmm0
; AVX512DQ-FCP-NEXT: vpermpd {{.*#+}} zmm1 = zmm1[0,3,2,3,4,7,6,7]
@@ -148,7 +148,7 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
;
; AVX512BW-FCP-LABEL: load_i64_stride3_vf2:
; AVX512BW-FCP: # %bb.0:
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} xmm0 = [1,4]
+; AVX512BW-FCP-NEXT: vpmovsxbq {{.*#+}} xmm0 = [1,4]
; AVX512BW-FCP-NEXT: vmovaps (%rdi), %zmm1
; AVX512BW-FCP-NEXT: vpermpd %zmm1, %zmm0, %zmm0
; AVX512BW-FCP-NEXT: vpermpd {{.*#+}} zmm1 = zmm1[0,3,2,3,4,7,6,7]
@@ -174,7 +174,7 @@ define void @load_i64_stride3_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
;
; AVX512DQ-BW-FCP-LABEL: load_i64_stride3_vf2:
; AVX512DQ-BW-FCP: # %bb.0:
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} xmm0 = [1,4]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbq {{.*#+}} xmm0 = [1,4]
; AVX512DQ-BW-FCP-NEXT: vmovaps (%rdi), %zmm1
; AVX512DQ-BW-FCP-NEXT: vpermpd %zmm1, %zmm0, %zmm0
; AVX512DQ-BW-FCP-NEXT: vpermpd {{.*#+}} zmm1 = zmm1[0,3,2,3,4,7,6,7]
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
index 6716d97b3f07c0..0c7c3f4b166461 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
@@ -120,7 +120,7 @@ define void @load_i64_stride4_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
;
; AVX512-FCP-LABEL: load_i64_stride4_vf2:
; AVX512-FCP: # %bb.0:
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0]
+; AVX512-FCP-NEXT: vpmovsxbq {{.*#+}} xmm0 = [0,4]
; AVX512-FCP-NEXT: vpermpd (%rdi), %zmm0, %zmm0
; AVX512-FCP-NEXT: vmovaps (%rdi), %xmm1
; AVX512-FCP-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1]
@@ -154,7 +154,7 @@ define void @load_i64_stride4_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
;
; AVX512DQ-FCP-LABEL: load_i64_stride4_vf2:
; AVX512DQ-FCP: # %bb.0:
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0]
+; AVX512DQ-FCP-NEXT: vpmovsxbq {{.*#+}} xmm0 = [0,4]
; AVX512DQ-FCP-NEXT: vpermpd (%rdi), %zmm0, %zmm0
; AVX512DQ-FCP-NEXT: vmovaps (%rdi), %xmm1
; AVX512DQ-FCP-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1]
@@ -188,7 +188,7 @@ define void @load_i64_stride4_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
;
; AVX512BW-FCP-LABEL: load_i64_stride4_vf2:
; AVX512BW-FCP: # %bb.0:
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0]
+; AVX512BW-FCP-NEXT: vpmovsxbq {{.*#+}} xmm0 = [0,4]
; AVX512BW-FCP-NEXT: vpermpd (%rdi), %zmm0, %zmm0
; AVX512BW-FCP-NEXT: vmovaps (%rdi), %xmm1
; AVX512BW-FCP-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1]
@@ -222,7 +222,7 @@ define void @load_i64_stride4_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
;
; AVX512DQ-BW-FCP-LABEL: load_i64_stride4_vf2:
; AVX512DQ-BW-FCP: # %bb.0:
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbq {{.*#+}} xmm0 = [0,4]
; AVX512DQ-BW-FCP-NEXT: vpermpd (%rdi), %zmm0, %zmm0
; AVX512DQ-BW-FCP-NEXT: vmovaps (%rdi), %xmm1
; AVX512DQ-BW-FCP-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm1[1],mem[1]
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
index e333e47219116d..47526e960328e7 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
@@ -186,7 +186,7 @@ define void @store_i32_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512: # %bb.0:
; AVX512-NEXT: vmovaps (%rdi), %xmm0
; AVX512-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
-; AVX512-NEXT: vmovaps {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
; AVX512-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512-NEXT: vmovaps %ymm0, (%rdx)
; AVX512-NEXT: vzeroupper
@@ -196,7 +196,7 @@ define void @store_i32_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512-FCP: # %bb.0:
; AVX512-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
; AVX512-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512-FCP-NEXT: vmovaps %ymm0, (%rdx)
; AVX512-FCP-NEXT: vzeroupper
@@ -206,7 +206,7 @@ define void @store_i32_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
-; AVX512DQ-NEXT: vmovaps {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
+; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
; AVX512DQ-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512DQ-NEXT: vmovaps %ymm0, (%rdx)
; AVX512DQ-NEXT: vzeroupper
@@ -216,7 +216,7 @@ define void @store_i32_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ-FCP: # %bb.0:
; AVX512DQ-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
; AVX512DQ-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512DQ-FCP-NEXT: vmovaps %ymm0, (%rdx)
; AVX512DQ-FCP-NEXT: vzeroupper
@@ -226,7 +226,7 @@ define void @store_i32_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovaps (%rdi), %xmm0
; AVX512BW-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
-; AVX512BW-NEXT: vmovaps {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
+; AVX512BW-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
; AVX512BW-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512BW-NEXT: vmovaps %ymm0, (%rdx)
; AVX512BW-NEXT: vzeroupper
@@ -236,7 +236,7 @@ define void @store_i32_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512BW-FCP: # %bb.0:
; AVX512BW-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512BW-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
+; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
; AVX512BW-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512BW-FCP-NEXT: vmovaps %ymm0, (%rdx)
; AVX512BW-FCP-NEXT: vzeroupper
@@ -246,7 +246,7 @@ define void @store_i32_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ-BW: # %bb.0:
; AVX512DQ-BW-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-BW-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
-; AVX512DQ-BW-NEXT: vmovaps {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
+; AVX512DQ-BW-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
; AVX512DQ-BW-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512DQ-BW-NEXT: vmovaps %ymm0, (%rdx)
; AVX512DQ-BW-NEXT: vzeroupper
@@ -256,7 +256,7 @@ define void @store_i32_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ-BW-FCP: # %bb.0:
; AVX512DQ-BW-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-BW-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,4,1,5,2,6,3,7]
; AVX512DQ-BW-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512DQ-BW-FCP-NEXT: vmovaps %ymm0, (%rdx)
; AVX512DQ-BW-FCP-NEXT: vzeroupper
@@ -348,7 +348,7 @@ define void @store_i32_stride2_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512: # %bb.0:
; AVX512-NEXT: vmovaps (%rdi), %ymm0
; AVX512-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
; AVX512-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512-NEXT: vmovaps %zmm0, (%rdx)
; AVX512-NEXT: vzeroupper
@@ -358,7 +358,7 @@ define void @store_i32_stride2_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512-FCP: # %bb.0:
; AVX512-FCP-NEXT: vmovaps (%rdi), %ymm0
; AVX512-FCP-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
; AVX512-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512-FCP-NEXT: vmovaps %zmm0, (%rdx)
; AVX512-FCP-NEXT: vzeroupper
@@ -368,7 +368,7 @@ define void @store_i32_stride2_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512DQ-NEXT: vmovaps {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
+; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
; AVX512DQ-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-NEXT: vmovaps %zmm0, (%rdx)
; AVX512DQ-NEXT: vzeroupper
@@ -378,7 +378,7 @@ define void @store_i32_stride2_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ-FCP: # %bb.0:
; AVX512DQ-FCP-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-FCP-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
; AVX512DQ-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-FCP-NEXT: vmovaps %zmm0, (%rdx)
; AVX512DQ-FCP-NEXT: vzeroupper
@@ -388,7 +388,7 @@ define void @store_i32_stride2_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovaps (%rdi), %ymm0
; AVX512BW-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
+; AVX512BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
; AVX512BW-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vmovaps %zmm0, (%rdx)
; AVX512BW-NEXT: vzeroupper
@@ -398,7 +398,7 @@ define void @store_i32_stride2_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512BW-FCP: # %bb.0:
; AVX512BW-FCP-NEXT: vmovaps (%rdi), %ymm0
; AVX512BW-FCP-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
+; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
; AVX512BW-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512BW-FCP-NEXT: vmovaps %zmm0, (%rdx)
; AVX512BW-FCP-NEXT: vzeroupper
@@ -408,7 +408,7 @@ define void @store_i32_stride2_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ-BW: # %bb.0:
; AVX512DQ-BW-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-BW-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512DQ-BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
+; AVX512DQ-BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
; AVX512DQ-BW-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-NEXT: vmovaps %zmm0, (%rdx)
; AVX512DQ-BW-NEXT: vzeroupper
@@ -418,7 +418,7 @@ define void @store_i32_stride2_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ-BW-FCP: # %bb.0:
; AVX512DQ-BW-FCP-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-BW-FCP-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,8,1,9,2,10,3,11,4,12,5,13,6,14,7,15]
; AVX512DQ-BW-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-FCP-NEXT: vmovaps %zmm0, (%rdx)
; AVX512DQ-BW-FCP-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
index 7037a2864654ff..f9228707182f72 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
@@ -100,7 +100,7 @@ define void @store_i32_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX512-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,1,3,5,u,u]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,1,3,5,0,0]
; AVX512-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512-NEXT: vmovlps %xmm1, 16(%rcx)
@@ -115,7 +115,7 @@ define void @store_i32_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-FCP-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512-FCP-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512-FCP-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,1,3,5,u,u]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,1,3,5,0,0]
; AVX512-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512-FCP-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512-FCP-NEXT: vmovlps %xmm1, 16(%rcx)
@@ -130,7 +130,7 @@ define void @store_i32_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512DQ-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512DQ-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX512DQ-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,1,3,5,u,u]
+; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,1,3,5,0,0]
; AVX512DQ-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512DQ-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512DQ-NEXT: vmovlps %xmm1, 16(%rcx)
@@ -145,7 +145,7 @@ define void @store_i32_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-FCP-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512DQ-FCP-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512DQ-FCP-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,1,3,5,u,u]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,1,3,5,0,0]
; AVX512DQ-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512DQ-FCP-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512DQ-FCP-NEXT: vmovlps %xmm1, 16(%rcx)
@@ -160,7 +160,7 @@ define void @store_i32_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512BW-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512BW-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX512BW-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,1,3,5,u,u]
+; AVX512BW-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,1,3,5,0,0]
; AVX512BW-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512BW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512BW-NEXT: vmovlps %xmm1, 16(%rcx)
@@ -175,7 +175,7 @@ define void @store_i32_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-FCP-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512BW-FCP-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512BW-FCP-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,1,3,5,u,u]
+; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,1,3,5,0,0]
; AVX512BW-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512BW-FCP-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512BW-FCP-NEXT: vmovlps %xmm1, 16(%rcx)
@@ -190,7 +190,7 @@ define void @store_i32_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512DQ-BW-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512DQ-BW-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX512DQ-BW-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,1,3,5,u,u]
+; AVX512DQ-BW-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,1,3,5,0,0]
; AVX512DQ-BW-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512DQ-BW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512DQ-BW-NEXT: vmovlps %xmm1, 16(%rcx)
@@ -205,7 +205,7 @@ define void @store_i32_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-FCP-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512DQ-BW-FCP-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512DQ-BW-FCP-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,1,3,5,u,u]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,1,3,5,0,0]
; AVX512DQ-BW-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512DQ-BW-FCP-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512DQ-BW-FCP-NEXT: vmovlps %xmm1, 16(%rcx)
@@ -321,7 +321,7 @@ define void @store_i32_stride3_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-NEXT: vmovaps (%rdi), %xmm0
; AVX512-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,u,u,u,u]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,0,0,0,0]
; AVX512-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512-NEXT: vmovaps %ymm0, (%rcx)
@@ -333,7 +333,7 @@ define void @store_i32_stride3_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512-FCP-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,u,u,u,u]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,0,0,0,0]
; AVX512-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512-FCP-NEXT: vmovaps %ymm0, (%rcx)
@@ -345,7 +345,7 @@ define void @store_i32_stride3_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512DQ-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,u,u,u,u]
+; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,0,0,0,0]
; AVX512DQ-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512DQ-NEXT: vmovaps %ymm0, (%rcx)
@@ -357,7 +357,7 @@ define void @store_i32_stride3_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-FCP-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,u,u,u,u]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,0,0,0,0]
; AVX512DQ-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512DQ-FCP-NEXT: vmovaps %ymm0, (%rcx)
@@ -369,7 +369,7 @@ define void @store_i32_stride3_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-NEXT: vmovaps (%rdi), %xmm0
; AVX512BW-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512BW-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,u,u,u,u]
+; AVX512BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,0,0,0,0]
; AVX512BW-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512BW-NEXT: vmovaps %ymm0, (%rcx)
@@ -381,7 +381,7 @@ define void @store_i32_stride3_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512BW-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512BW-FCP-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,u,u,u,u]
+; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,0,0,0,0]
; AVX512BW-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512BW-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512BW-FCP-NEXT: vmovaps %ymm0, (%rcx)
@@ -393,7 +393,7 @@ define void @store_i32_stride3_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-BW-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-BW-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512DQ-BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,u,u,u,u]
+; AVX512DQ-BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,0,0,0,0]
; AVX512DQ-BW-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512DQ-BW-NEXT: vmovaps %ymm0, (%rcx)
@@ -405,7 +405,7 @@ define void @store_i32_stride3_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-BW-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-BW-FCP-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,u,u,u,u]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,1,5,9,2,6,10,3,7,11,0,0,0,0]
; AVX512DQ-BW-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512DQ-BW-FCP-NEXT: vmovaps %ymm0, (%rcx)
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
index 4beed72f22e33f..22040e0cdb791a 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
@@ -117,7 +117,7 @@ define void @store_i32_stride4_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-FCP-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512-FCP-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,6,1,3,5,7]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,6,1,3,5,7]
; AVX512-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512-FCP-NEXT: vmovaps %ymm0, (%r8)
; AVX512-FCP-NEXT: vzeroupper
@@ -147,7 +147,7 @@ define void @store_i32_stride4_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-FCP-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512DQ-FCP-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512DQ-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,6,1,3,5,7]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,6,1,3,5,7]
; AVX512DQ-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512DQ-FCP-NEXT: vmovaps %ymm0, (%r8)
; AVX512DQ-FCP-NEXT: vzeroupper
@@ -177,7 +177,7 @@ define void @store_i32_stride4_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-FCP-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512BW-FCP-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512BW-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,6,1,3,5,7]
+; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,6,1,3,5,7]
; AVX512BW-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512BW-FCP-NEXT: vmovaps %ymm0, (%r8)
; AVX512BW-FCP-NEXT: vzeroupper
@@ -207,7 +207,7 @@ define void @store_i32_stride4_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-FCP-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX512DQ-BW-FCP-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512DQ-BW-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} ymm1 = [0,2,4,6,1,3,5,7]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,2,4,6,1,3,5,7]
; AVX512DQ-BW-FCP-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512DQ-BW-FCP-NEXT: vmovaps %ymm0, (%r8)
; AVX512DQ-BW-FCP-NEXT: vzeroupper
@@ -346,7 +346,7 @@ define void @store_i32_stride4_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX512-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
; AVX512-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512-NEXT: vmovaps %zmm0, (%r8)
; AVX512-NEXT: vzeroupper
@@ -359,7 +359,7 @@ define void @store_i32_stride4_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-FCP-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX512-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512-FCP-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
; AVX512-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512-FCP-NEXT: vmovaps %zmm0, (%r8)
; AVX512-FCP-NEXT: vzeroupper
@@ -372,7 +372,7 @@ define void @store_i32_stride4_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX512DQ-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512DQ-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
+; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
; AVX512DQ-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-NEXT: vmovaps %zmm0, (%r8)
; AVX512DQ-NEXT: vzeroupper
@@ -385,7 +385,7 @@ define void @store_i32_stride4_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-FCP-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX512DQ-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-FCP-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
; AVX512DQ-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-FCP-NEXT: vmovaps %zmm0, (%r8)
; AVX512DQ-FCP-NEXT: vzeroupper
@@ -398,7 +398,7 @@ define void @store_i32_stride4_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX512BW-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512BW-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
+; AVX512BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
; AVX512BW-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vmovaps %zmm0, (%r8)
; AVX512BW-NEXT: vzeroupper
@@ -411,7 +411,7 @@ define void @store_i32_stride4_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-FCP-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX512BW-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512BW-FCP-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
+; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
; AVX512BW-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512BW-FCP-NEXT: vmovaps %zmm0, (%r8)
; AVX512BW-FCP-NEXT: vzeroupper
@@ -424,7 +424,7 @@ define void @store_i32_stride4_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX512DQ-BW-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-BW-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512DQ-BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
+; AVX512DQ-BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
; AVX512DQ-BW-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-NEXT: vmovaps %zmm0, (%r8)
; AVX512DQ-BW-NEXT: vzeroupper
@@ -437,7 +437,7 @@ define void @store_i32_stride4_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-FCP-NEXT: vinsertf128 $1, (%rcx), %ymm1, %ymm1
; AVX512DQ-BW-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-BW-FCP-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,4,8,12,1,5,9,13,2,6,10,14,3,7,11,15]
; AVX512DQ-BW-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-FCP-NEXT: vmovaps %zmm0, (%r8)
; AVX512DQ-BW-FCP-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
index b6914ec1973004..07d8a370a5f930 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
@@ -142,7 +142,7 @@ define void @store_i32_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX512-NEXT: vinsertf32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,u,u,u,u,u,u]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,0,0,0,0,0,0]
; AVX512-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512-NEXT: vextractf32x4 $2, %zmm0, %xmm1
; AVX512-NEXT: vmovlps %xmm1, 32(%r9)
@@ -161,7 +161,7 @@ define void @store_i32_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-FCP-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX512-FCP-NEXT: vinsertf32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,u,u,u,u,u,u]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,0,0,0,0,0,0]
; AVX512-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512-FCP-NEXT: vextractf32x4 $2, %zmm0, %xmm1
; AVX512-FCP-NEXT: vmovlps %xmm1, 32(%r9)
@@ -180,7 +180,7 @@ define void @store_i32_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512DQ-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX512DQ-NEXT: vinsertf32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512DQ-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,u,u,u,u,u,u]
+; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,0,0,0,0,0,0]
; AVX512DQ-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-NEXT: vextractf32x4 $2, %zmm0, %xmm1
; AVX512DQ-NEXT: vmovlps %xmm1, 32(%r9)
@@ -199,7 +199,7 @@ define void @store_i32_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512DQ-FCP-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX512DQ-FCP-NEXT: vinsertf32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,u,u,u,u,u,u]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,0,0,0,0,0,0]
; AVX512DQ-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-FCP-NEXT: vextractf32x4 $2, %zmm0, %xmm1
; AVX512DQ-FCP-NEXT: vmovlps %xmm1, 32(%r9)
@@ -218,7 +218,7 @@ define void @store_i32_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512BW-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX512BW-NEXT: vinsertf32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,u,u,u,u,u,u]
+; AVX512BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,0,0,0,0,0,0]
; AVX512BW-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vextractf32x4 $2, %zmm0, %xmm1
; AVX512BW-NEXT: vmovlps %xmm1, 32(%r9)
@@ -237,7 +237,7 @@ define void @store_i32_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512BW-FCP-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX512BW-FCP-NEXT: vinsertf32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,u,u,u,u,u,u]
+; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,0,0,0,0,0,0]
; AVX512BW-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512BW-FCP-NEXT: vextractf32x4 $2, %zmm0, %xmm1
; AVX512BW-FCP-NEXT: vmovlps %xmm1, 32(%r9)
@@ -256,7 +256,7 @@ define void @store_i32_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512DQ-BW-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX512DQ-BW-NEXT: vinsertf32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512DQ-BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,u,u,u,u,u,u]
+; AVX512DQ-BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,0,0,0,0,0,0]
; AVX512DQ-BW-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-NEXT: vextractf32x4 $2, %zmm0, %xmm1
; AVX512DQ-BW-NEXT: vmovlps %xmm1, 32(%r9)
@@ -275,7 +275,7 @@ define void @store_i32_stride5_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512DQ-BW-FCP-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX512DQ-BW-FCP-NEXT: vinsertf32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,u,u,u,u,u,u]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,1,3,5,7,9,0,0,0,0,0,0]
; AVX512DQ-BW-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-FCP-NEXT: vextractf32x4 $2, %zmm0, %xmm1
; AVX512DQ-BW-FCP-NEXT: vmovlps %xmm1, 32(%r9)
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
index 9d53325ed7c56f..78b07e5671e5ad 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
@@ -152,7 +152,7 @@ define void @store_i32_stride6_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: vinsertf32x4 $2, %xmm2, %zmm0, %zmm0
-; AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,u,u,u,u]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,0,0,0,0]
; AVX512-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512-NEXT: vextractf32x4 $2, %zmm0, 32(%rax)
; AVX512-NEXT: vmovaps %ymm0, (%rax)
@@ -173,7 +173,7 @@ define void @store_i32_stride6_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-FCP-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-FCP-NEXT: vinsertf32x4 $2, %xmm2, %zmm0, %zmm0
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,u,u,u,u]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,0,0,0,0]
; AVX512-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rax)
; AVX512-FCP-NEXT: vmovaps %ymm0, (%rax)
@@ -194,7 +194,7 @@ define void @store_i32_stride6_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512DQ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512DQ-NEXT: vinsertf32x4 $2, %xmm2, %zmm0, %zmm0
-; AVX512DQ-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,u,u,u,u]
+; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,0,0,0,0]
; AVX512DQ-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-NEXT: vextractf32x4 $2, %zmm0, 32(%rax)
; AVX512DQ-NEXT: vmovaps %ymm0, (%rax)
@@ -215,7 +215,7 @@ define void @store_i32_stride6_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-FCP-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512DQ-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512DQ-FCP-NEXT: vinsertf32x4 $2, %xmm2, %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,u,u,u,u]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,0,0,0,0]
; AVX512DQ-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rax)
; AVX512DQ-FCP-NEXT: vmovaps %ymm0, (%rax)
@@ -236,7 +236,7 @@ define void @store_i32_stride6_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512BW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512BW-NEXT: vinsertf32x4 $2, %xmm2, %zmm0, %zmm0
-; AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,u,u,u,u]
+; AVX512BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,0,0,0,0]
; AVX512BW-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vextractf32x4 $2, %zmm0, 32(%rax)
; AVX512BW-NEXT: vmovaps %ymm0, (%rax)
@@ -257,7 +257,7 @@ define void @store_i32_stride6_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-FCP-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512BW-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512BW-FCP-NEXT: vinsertf32x4 $2, %xmm2, %zmm0, %zmm0
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,u,u,u,u]
+; AVX512BW-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,0,0,0,0]
; AVX512BW-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512BW-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rax)
; AVX512BW-FCP-NEXT: vmovaps %ymm0, (%rax)
@@ -278,7 +278,7 @@ define void @store_i32_stride6_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512DQ-BW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512DQ-BW-NEXT: vinsertf32x4 $2, %xmm2, %zmm0, %zmm0
-; AVX512DQ-BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,u,u,u,u]
+; AVX512DQ-BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,0,0,0,0]
; AVX512DQ-BW-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-NEXT: vextractf32x4 $2, %zmm0, 32(%rax)
; AVX512DQ-BW-NEXT: vmovaps %ymm0, (%rax)
@@ -299,7 +299,7 @@ define void @store_i32_stride6_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-FCP-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512DQ-BW-FCP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512DQ-BW-FCP-NEXT: vinsertf32x4 $2, %xmm2, %zmm0, %zmm0
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,u,u,u,u]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,2,4,6,8,10,1,3,5,7,9,11,0,0,0,0]
; AVX512DQ-BW-FCP-NEXT: vpermps %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rax)
; AVX512DQ-BW-FCP-NEXT: vmovaps %ymm0, (%rax)
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
index 67b447ed5d014f..1061c08dcceda2 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
@@ -225,7 +225,7 @@ define void @store_i64_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512: # %bb.0:
; AVX512-NEXT: vmovaps (%rdi), %ymm0
; AVX512-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
; AVX512-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512-NEXT: vmovaps %zmm0, (%rdx)
; AVX512-NEXT: vzeroupper
@@ -235,7 +235,7 @@ define void @store_i64_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512-FCP: # %bb.0:
; AVX512-FCP-NEXT: vmovaps (%rdi), %ymm0
; AVX512-FCP-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
+; AVX512-FCP-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
; AVX512-FCP-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512-FCP-NEXT: vmovaps %zmm0, (%rdx)
; AVX512-FCP-NEXT: vzeroupper
@@ -245,7 +245,7 @@ define void @store_i64_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512DQ-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
+; AVX512DQ-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
; AVX512DQ-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512DQ-NEXT: vmovaps %zmm0, (%rdx)
; AVX512DQ-NEXT: vzeroupper
@@ -255,7 +255,7 @@ define void @store_i64_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ-FCP: # %bb.0:
; AVX512DQ-FCP-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-FCP-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
+; AVX512DQ-FCP-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
; AVX512DQ-FCP-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512DQ-FCP-NEXT: vmovaps %zmm0, (%rdx)
; AVX512DQ-FCP-NEXT: vzeroupper
@@ -265,7 +265,7 @@ define void @store_i64_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovaps (%rdi), %ymm0
; AVX512BW-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
+; AVX512BW-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
; AVX512BW-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vmovaps %zmm0, (%rdx)
; AVX512BW-NEXT: vzeroupper
@@ -275,7 +275,7 @@ define void @store_i64_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512BW-FCP: # %bb.0:
; AVX512BW-FCP-NEXT: vmovaps (%rdi), %ymm0
; AVX512BW-FCP-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
+; AVX512BW-FCP-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
; AVX512BW-FCP-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512BW-FCP-NEXT: vmovaps %zmm0, (%rdx)
; AVX512BW-FCP-NEXT: vzeroupper
@@ -285,7 +285,7 @@ define void @store_i64_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ-BW: # %bb.0:
; AVX512DQ-BW-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-BW-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512DQ-BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
+; AVX512DQ-BW-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
; AVX512DQ-BW-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-NEXT: vmovaps %zmm0, (%rdx)
; AVX512DQ-BW-NEXT: vzeroupper
@@ -295,7 +295,7 @@ define void @store_i64_stride2_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %out.ve
; AVX512DQ-BW-FCP: # %bb.0:
; AVX512DQ-BW-FCP-NEXT: vmovaps (%rdi), %ymm0
; AVX512DQ-BW-FCP-NEXT: vinsertf64x4 $1, (%rsi), %zmm0, %zmm0
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,4,1,5,2,6,3,7]
; AVX512DQ-BW-FCP-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-FCP-NEXT: vmovaps %zmm0, (%rdx)
; AVX512DQ-BW-FCP-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
index a01d4de0027f40..fe39c769c35459 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
@@ -94,7 +94,7 @@ define void @store_i64_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-NEXT: vmovaps (%rdi), %xmm0
; AVX512-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,1,3,5,u,u]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,2,4,1,3,5,0,0]
; AVX512-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512-NEXT: vmovaps %ymm0, (%rcx)
@@ -106,7 +106,7 @@ define void @store_i64_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512-FCP-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,1,3,5,u,u]
+; AVX512-FCP-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,2,4,1,3,5,0,0]
; AVX512-FCP-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512-FCP-NEXT: vmovaps %ymm0, (%rcx)
@@ -118,7 +118,7 @@ define void @store_i64_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512DQ-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,1,3,5,u,u]
+; AVX512DQ-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,2,4,1,3,5,0,0]
; AVX512DQ-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512DQ-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512DQ-NEXT: vmovaps %ymm0, (%rcx)
@@ -130,7 +130,7 @@ define void @store_i64_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-FCP-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,1,3,5,u,u]
+; AVX512DQ-FCP-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,2,4,1,3,5,0,0]
; AVX512DQ-FCP-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512DQ-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512DQ-FCP-NEXT: vmovaps %ymm0, (%rcx)
@@ -142,7 +142,7 @@ define void @store_i64_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-NEXT: vmovaps (%rdi), %xmm0
; AVX512BW-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512BW-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,1,3,5,u,u]
+; AVX512BW-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,2,4,1,3,5,0,0]
; AVX512BW-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512BW-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512BW-NEXT: vmovaps %ymm0, (%rcx)
@@ -154,7 +154,7 @@ define void @store_i64_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512BW-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512BW-FCP-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,1,3,5,u,u]
+; AVX512BW-FCP-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,2,4,1,3,5,0,0]
; AVX512BW-FCP-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512BW-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512BW-FCP-NEXT: vmovaps %ymm0, (%rcx)
@@ -166,7 +166,7 @@ define void @store_i64_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-BW-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-BW-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512DQ-BW-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,1,3,5,u,u]
+; AVX512DQ-BW-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,2,4,1,3,5,0,0]
; AVX512DQ-BW-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512DQ-BW-NEXT: vmovaps %ymm0, (%rcx)
@@ -178,7 +178,7 @@ define void @store_i64_stride3_vf2(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-FCP-NEXT: vmovaps (%rdi), %xmm0
; AVX512DQ-BW-FCP-NEXT: vinsertf128 $1, (%rsi), %ymm0, %ymm0
; AVX512DQ-BW-FCP-NEXT: vinsertf32x4 $2, (%rdx), %zmm0, %zmm0
-; AVX512DQ-BW-FCP-NEXT: vmovaps {{.*#+}} zmm1 = [0,2,4,1,3,5,u,u]
+; AVX512DQ-BW-FCP-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,2,4,1,3,5,0,0]
; AVX512DQ-BW-FCP-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512DQ-BW-FCP-NEXT: vextractf32x4 $2, %zmm0, 32(%rcx)
; AVX512DQ-BW-FCP-NEXT: vmovaps %ymm0, (%rcx)
diff --git a/llvm/test/CodeGen/X86/vector-lzcnt-128.ll b/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
index 5d02bb8b05f181..cfb5fac2fd7aa8 100644
--- a/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
@@ -1815,16 +1815,26 @@ define <2 x i64> @foldv2i64() nounwind {
; SSE-NEXT: movss {{.*#+}} xmm0 = [55,0,0,0]
; SSE-NEXT: retq
;
-; NOBW-LABEL: foldv2i64:
-; NOBW: # %bb.0:
-; NOBW-NEXT: vmovss {{.*#+}} xmm0 = [55,0,0,0]
-; NOBW-NEXT: retq
+; AVX1OR2-LABEL: foldv2i64:
+; AVX1OR2: # %bb.0:
+; AVX1OR2-NEXT: vmovss {{.*#+}} xmm0 = [55,0,0,0]
+; AVX1OR2-NEXT: retq
+;
+; AVX512VL-LABEL: foldv2i64:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} xmm0 = [55,0]
+; AVX512VL-NEXT: retq
;
; AVX512VLBWDQ-LABEL: foldv2i64:
; AVX512VLBWDQ: # %bb.0:
-; AVX512VLBWDQ-NEXT: vmovss {{.*#+}} xmm0 = [55,0,0,0]
+; AVX512VLBWDQ-NEXT: vpmovsxbq {{.*#+}} xmm0 = [55,0]
; AVX512VLBWDQ-NEXT: retq
;
+; AVX512-LABEL: foldv2i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [55,0]
+; AVX512-NEXT: retq
+;
; X86-SSE-LABEL: foldv2i64:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = [55,0,0,0]
@@ -1839,16 +1849,26 @@ define <2 x i64> @foldv2i64u() nounwind {
; SSE-NEXT: movss {{.*#+}} xmm0 = [55,0,0,0]
; SSE-NEXT: retq
;
-; NOBW-LABEL: foldv2i64u:
-; NOBW: # %bb.0:
-; NOBW-NEXT: vmovss {{.*#+}} xmm0 = [55,0,0,0]
-; NOBW-NEXT: retq
+; AVX1OR2-LABEL: foldv2i64u:
+; AVX1OR2: # %bb.0:
+; AVX1OR2-NEXT: vmovss {{.*#+}} xmm0 = [55,0,0,0]
+; AVX1OR2-NEXT: retq
+;
+; AVX512VL-LABEL: foldv2i64u:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} xmm0 = [55,0]
+; AVX512VL-NEXT: retq
;
; AVX512VLBWDQ-LABEL: foldv2i64u:
; AVX512VLBWDQ: # %bb.0:
-; AVX512VLBWDQ-NEXT: vmovss {{.*#+}} xmm0 = [55,0,0,0]
+; AVX512VLBWDQ-NEXT: vpmovsxbq {{.*#+}} xmm0 = [55,0]
; AVX512VLBWDQ-NEXT: retq
;
+; AVX512-LABEL: foldv2i64u:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [55,0]
+; AVX512-NEXT: retq
+;
; X86-SSE-LABEL: foldv2i64u:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = [55,0,0,0]
@@ -1863,16 +1883,26 @@ define <4 x i32> @foldv4i32() nounwind {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [23,0,32,24]
; SSE-NEXT: retq
;
-; NOBW-LABEL: foldv4i32:
-; NOBW: # %bb.0:
-; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [23,0,32,24]
-; NOBW-NEXT: retq
+; AVX1OR2-LABEL: foldv4i32:
+; AVX1OR2: # %bb.0:
+; AVX1OR2-NEXT: vmovaps {{.*#+}} xmm0 = [23,0,32,24]
+; AVX1OR2-NEXT: retq
+;
+; AVX512VL-LABEL: foldv4i32:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm0 = [23,0,32,24]
+; AVX512VL-NEXT: retq
;
; AVX512VLBWDQ-LABEL: foldv4i32:
; AVX512VLBWDQ: # %bb.0:
-; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [23,0,32,24]
+; AVX512VLBWDQ-NEXT: vpmovsxbd {{.*#+}} xmm0 = [23,0,32,24]
; AVX512VLBWDQ-NEXT: retq
;
+; AVX512-LABEL: foldv4i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [23,0,32,24]
+; AVX512-NEXT: retq
+;
; X86-SSE-LABEL: foldv4i32:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movaps {{.*#+}} xmm0 = [23,0,32,24]
@@ -1887,16 +1917,26 @@ define <4 x i32> @foldv4i32u() nounwind {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [23,0,32,24]
; SSE-NEXT: retq
;
-; NOBW-LABEL: foldv4i32u:
-; NOBW: # %bb.0:
-; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [23,0,32,24]
-; NOBW-NEXT: retq
+; AVX1OR2-LABEL: foldv4i32u:
+; AVX1OR2: # %bb.0:
+; AVX1OR2-NEXT: vmovaps {{.*#+}} xmm0 = [23,0,32,24]
+; AVX1OR2-NEXT: retq
+;
+; AVX512VL-LABEL: foldv4i32u:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm0 = [23,0,32,24]
+; AVX512VL-NEXT: retq
;
; AVX512VLBWDQ-LABEL: foldv4i32u:
; AVX512VLBWDQ: # %bb.0:
-; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [23,0,32,24]
+; AVX512VLBWDQ-NEXT: vpmovsxbd {{.*#+}} xmm0 = [23,0,32,24]
; AVX512VLBWDQ-NEXT: retq
;
+; AVX512-LABEL: foldv4i32u:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [23,0,32,24]
+; AVX512-NEXT: retq
+;
; X86-SSE-LABEL: foldv4i32u:
; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movaps {{.*#+}} xmm0 = [23,0,32,24]
diff --git a/llvm/test/CodeGen/X86/vector-lzcnt-256.ll b/llvm/test/CodeGen/X86/vector-lzcnt-256.ll
index 8a0d9a6134cea5..db363493e2dac9 100644
--- a/llvm/test/CodeGen/X86/vector-lzcnt-256.ll
+++ b/llvm/test/CodeGen/X86/vector-lzcnt-256.ll
@@ -1128,10 +1128,30 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind {
}
define <4 x i64> @foldv4i64() nounwind {
-; X64-LABEL: foldv4i64:
-; X64: # %bb.0:
-; X64-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,64,56]
-; X64-NEXT: retq
+; AVX1-LABEL: foldv4i64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,64,56]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv4i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,64,56]
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: foldv4i64:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} ymm0 = [55,0,64,56]
+; AVX512VL-NEXT: retq
+;
+; AVX512VLBWDQ-LABEL: foldv4i64:
+; AVX512VLBWDQ: # %bb.0:
+; AVX512VLBWDQ-NEXT: vpmovsxbq {{.*#+}} ymm0 = [55,0,64,56]
+; AVX512VLBWDQ-NEXT: retq
+;
+; AVX512-LABEL: foldv4i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [55,0,64,56]
+; AVX512-NEXT: retq
;
; X86-AVX-LABEL: foldv4i64:
; X86-AVX: # %bb.0:
@@ -1142,10 +1162,30 @@ define <4 x i64> @foldv4i64() nounwind {
}
define <4 x i64> @foldv4i64u() nounwind {
-; X64-LABEL: foldv4i64u:
-; X64: # %bb.0:
-; X64-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,64,56]
-; X64-NEXT: retq
+; AVX1-LABEL: foldv4i64u:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,64,56]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv4i64u:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [55,0,64,56]
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: foldv4i64u:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} ymm0 = [55,0,64,56]
+; AVX512VL-NEXT: retq
+;
+; AVX512VLBWDQ-LABEL: foldv4i64u:
+; AVX512VLBWDQ: # %bb.0:
+; AVX512VLBWDQ-NEXT: vpmovsxbq {{.*#+}} ymm0 = [55,0,64,56]
+; AVX512VLBWDQ-NEXT: retq
+;
+; AVX512-LABEL: foldv4i64u:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [55,0,64,56]
+; AVX512-NEXT: retq
;
; X86-AVX-LABEL: foldv4i64u:
; X86-AVX: # %bb.0:
@@ -1156,10 +1196,30 @@ define <4 x i64> @foldv4i64u() nounwind {
}
define <8 x i32> @foldv8i32() nounwind {
-; X64-LABEL: foldv8i32:
-; X64: # %bb.0:
-; X64-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
-; X64-NEXT: retq
+; AVX1-LABEL: foldv8i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv8i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: foldv8i32:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
+; AVX512VL-NEXT: retq
+;
+; AVX512VLBWDQ-LABEL: foldv8i32:
+; AVX512VLBWDQ: # %bb.0:
+; AVX512VLBWDQ-NEXT: vpmovsxbd {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
+; AVX512VLBWDQ-NEXT: retq
+;
+; AVX512-LABEL: foldv8i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
+; AVX512-NEXT: retq
;
; X86-AVX-LABEL: foldv8i32:
; X86-AVX: # %bb.0:
@@ -1170,10 +1230,30 @@ define <8 x i32> @foldv8i32() nounwind {
}
define <8 x i32> @foldv8i32u() nounwind {
-; X64-LABEL: foldv8i32u:
-; X64: # %bb.0:
-; X64-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
-; X64-NEXT: retq
+; AVX1-LABEL: foldv8i32u:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv8i32u:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: foldv8i32u:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
+; AVX512VL-NEXT: retq
+;
+; AVX512VLBWDQ-LABEL: foldv8i32u:
+; AVX512VLBWDQ: # %bb.0:
+; AVX512VLBWDQ-NEXT: vpmovsxbd {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
+; AVX512VLBWDQ-NEXT: retq
+;
+; AVX512-LABEL: foldv8i32u:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [23,0,32,24,0,29,27,25]
+; AVX512-NEXT: retq
;
; X86-AVX-LABEL: foldv8i32u:
; X86-AVX: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-128.ll b/llvm/test/CodeGen/X86/vector-popcnt-128.ll
index e178ab0348a765..741d70a3690225 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-128.ll
@@ -629,19 +629,29 @@ define <2 x i64> @foldv2i64() nounwind {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,64]
; SSE-NEXT: retq
;
-; AVX-LABEL: foldv2i64:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,64]
-; AVX-NEXT: retq
+; AVX1OR2-LABEL: foldv2i64:
+; AVX1OR2: # %bb.0:
+; AVX1OR2-NEXT: vmovaps {{.*#+}} xmm0 = [1,64]
+; AVX1OR2-NEXT: retq
+;
+; XOP-LABEL: foldv2i64:
+; XOP: # %bb.0:
+; XOP-NEXT: vmovaps {{.*#+}} xmm0 = [1,64]
+; XOP-NEXT: retq
+;
+; AVX512-LABEL: foldv2i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbq {{.*#+}} xmm0 = [1,64]
+; AVX512-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv2i64:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [1,64]
+; BITALG_NOVLX-NEXT: vpmovsxbq {{.*#+}} xmm0 = [1,64]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv2i64:
; BITALG: # %bb.0:
-; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [1,64]
+; BITALG-NEXT: vpmovsxbq {{.*#+}} xmm0 = [1,64]
; BITALG-NEXT: retq
%out = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> <i64 256, i64 -1>)
ret <2 x i64> %out
@@ -653,19 +663,29 @@ define <4 x i32> @foldv4i32() nounwind {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,32,0,8]
; SSE-NEXT: retq
;
-; AVX-LABEL: foldv4i32:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,32,0,8]
-; AVX-NEXT: retq
+; AVX1OR2-LABEL: foldv4i32:
+; AVX1OR2: # %bb.0:
+; AVX1OR2-NEXT: vmovaps {{.*#+}} xmm0 = [1,32,0,8]
+; AVX1OR2-NEXT: retq
+;
+; XOP-LABEL: foldv4i32:
+; XOP: # %bb.0:
+; XOP-NEXT: vmovaps {{.*#+}} xmm0 = [1,32,0,8]
+; XOP-NEXT: retq
+;
+; AVX512-LABEL: foldv4i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm0 = [1,32,0,8]
+; AVX512-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv4i32:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [1,32,0,8]
+; BITALG_NOVLX-NEXT: vpmovsxbd {{.*#+}} xmm0 = [1,32,0,8]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv4i32:
; BITALG: # %bb.0:
-; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [1,32,0,8]
+; BITALG-NEXT: vpmovsxbd {{.*#+}} xmm0 = [1,32,0,8]
; BITALG-NEXT: retq
%out = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> <i32 256, i32 -1, i32 0, i32 255>)
ret <4 x i32> %out
diff --git a/llvm/test/CodeGen/X86/vector-popcnt-256.ll b/llvm/test/CodeGen/X86/vector-popcnt-256.ll
index 6c45742730a622..701b9622089db8 100644
--- a/llvm/test/CodeGen/X86/vector-popcnt-256.ll
+++ b/llvm/test/CodeGen/X86/vector-popcnt-256.ll
@@ -409,19 +409,79 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind {
}
define <4 x i64> @foldv4i64() nounwind {
-; ALL-LABEL: foldv4i64:
-; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} ymm0 = [1,64,0,8]
-; ALL-NEXT: retq
+; AVX1-LABEL: foldv4i64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [1,64,0,8]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv4i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [1,64,0,8]
+; AVX2-NEXT: retq
+;
+; XOP-LABEL: foldv4i64:
+; XOP: # %bb.0:
+; XOP-NEXT: vmovaps {{.*#+}} ymm0 = [1,64,0,8]
+; XOP-NEXT: retq
+;
+; AVX512VPOPCNTDQ-LABEL: foldv4i64:
+; AVX512VPOPCNTDQ: # %bb.0:
+; AVX512VPOPCNTDQ-NEXT: vpmovsxbq {{.*#+}} ymm0 = [1,64,0,8]
+; AVX512VPOPCNTDQ-NEXT: retq
+;
+; AVX512VPOPCNTDQVL-LABEL: foldv4i64:
+; AVX512VPOPCNTDQVL: # %bb.0:
+; AVX512VPOPCNTDQVL-NEXT: vpmovsxbq {{.*#+}} ymm0 = [1,64,0,8]
+; AVX512VPOPCNTDQVL-NEXT: retq
+;
+; BITALG_NOVLX-LABEL: foldv4i64:
+; BITALG_NOVLX: # %bb.0:
+; BITALG_NOVLX-NEXT: vpmovsxbq {{.*#+}} ymm0 = [1,64,0,8]
+; BITALG_NOVLX-NEXT: retq
+;
+; BITALG-LABEL: foldv4i64:
+; BITALG: # %bb.0:
+; BITALG-NEXT: vpmovsxbq {{.*#+}} ymm0 = [1,64,0,8]
+; BITALG-NEXT: retq
%out = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> <i64 256, i64 -1, i64 0, i64 255>)
ret <4 x i64> %out
}
define <8 x i32> @foldv8i32() nounwind {
-; ALL-LABEL: foldv8i32:
-; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} ymm0 = [1,32,0,8,16,3,2,3]
-; ALL-NEXT: retq
+; AVX1-LABEL: foldv8i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [1,32,0,8,16,3,2,3]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv8i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [1,32,0,8,16,3,2,3]
+; AVX2-NEXT: retq
+;
+; XOP-LABEL: foldv8i32:
+; XOP: # %bb.0:
+; XOP-NEXT: vmovaps {{.*#+}} ymm0 = [1,32,0,8,16,3,2,3]
+; XOP-NEXT: retq
+;
+; AVX512VPOPCNTDQ-LABEL: foldv8i32:
+; AVX512VPOPCNTDQ: # %bb.0:
+; AVX512VPOPCNTDQ-NEXT: vpmovsxbd {{.*#+}} ymm0 = [1,32,0,8,16,3,2,3]
+; AVX512VPOPCNTDQ-NEXT: retq
+;
+; AVX512VPOPCNTDQVL-LABEL: foldv8i32:
+; AVX512VPOPCNTDQVL: # %bb.0:
+; AVX512VPOPCNTDQVL-NEXT: vpmovsxbd {{.*#+}} ymm0 = [1,32,0,8,16,3,2,3]
+; AVX512VPOPCNTDQVL-NEXT: retq
+;
+; BITALG_NOVLX-LABEL: foldv8i32:
+; BITALG_NOVLX: # %bb.0:
+; BITALG_NOVLX-NEXT: vpmovsxbd {{.*#+}} ymm0 = [1,32,0,8,16,3,2,3]
+; BITALG_NOVLX-NEXT: retq
+;
+; BITALG-LABEL: foldv8i32:
+; BITALG: # %bb.0:
+; BITALG-NEXT: vpmovsxbd {{.*#+}} ymm0 = [1,32,0,8,16,3,2,3]
+; BITALG-NEXT: retq
%out = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> <i32 256, i32 -1, i32 0, i32 255, i32 -65536, i32 7, i32 24, i32 88>)
ret <8 x i32> %out
}
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll b/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
index 025518d1a101eb..a79b109feec72b 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
@@ -2516,7 +2516,7 @@ define <4 x float> @shuffle_mem_v4f32_0624(<4 x float> %a0, ptr %a1) {
;
; AVX512VL-LABEL: shuffle_mem_v4f32_0624:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovaps {{.*#+}} xmm1 = [4,2,6,0]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm1 = [4,2,6,0]
; AVX512VL-NEXT: vpermt2ps (%rdi), %xmm1, %xmm0
; AVX512VL-NEXT: retq
%1 = load <4 x float>, ptr %a1
@@ -2540,7 +2540,7 @@ define <4 x float> @shuffle_mem_v4f32_4760(<4 x float> %a0, ptr %a1) {
;
; AVX512VL-LABEL: shuffle_mem_v4f32_4760:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovaps {{.*#+}} xmm1 = [0,3,2,4]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,3,2,4]
; AVX512VL-NEXT: vpermt2ps (%rdi), %xmm1, %xmm0
; AVX512VL-NEXT: retq
%1 = load <4 x float>, ptr %a1
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
index 919869df6c2629..81f79f3b1399a4 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
@@ -332,7 +332,7 @@ define <4 x double> @shuffle_v4f64_0423(<4 x double> %a, <4 x double> %b) {
;
; AVX512VL-FAST-LABEL: shuffle_v4f64_0423:
; AVX512VL-FAST: # %bb.0:
-; AVX512VL-FAST-NEXT: vmovapd {{.*#+}} ymm2 = [0,4,2,3]
+; AVX512VL-FAST-NEXT: vpmovsxbq {{.*#+}} ymm2 = [0,4,2,3]
; AVX512VL-FAST-NEXT: vpermt2pd %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
@@ -349,7 +349,7 @@ define <4 x double> @shuffle_v4f64_0462(<4 x double> %a, <4 x double> %b) {
;
; AVX512VL-LABEL: shuffle_v4f64_0462:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovapd {{.*#+}} ymm2 = [0,4,6,2]
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} ymm2 = [0,4,6,2]
; AVX512VL-NEXT: vpermt2pd %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 6, i32 2>
@@ -461,7 +461,7 @@ define <4 x double> @shuffle_v4f64_1054(<4 x double> %a, <4 x double> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v4f64_1054:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovapd {{.*#+}} ymm2 = [1,0,5,4]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbq {{.*#+}} ymm2 = [1,0,5,4]
; AVX512VL-FAST-ALL-NEXT: vpermt2pd %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -489,7 +489,7 @@ define <4 x double> @shuffle_v4f64_3254(<4 x double> %a, <4 x double> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v4f64_3254:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovapd {{.*#+}} ymm2 = [3,2,5,4]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbq {{.*#+}} ymm2 = [3,2,5,4]
; AVX512VL-FAST-ALL-NEXT: vpermt2pd %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -517,7 +517,7 @@ define <4 x double> @shuffle_v4f64_3276(<4 x double> %a, <4 x double> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v4f64_3276:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovapd {{.*#+}} ymm2 = [3,2,7,6]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbq {{.*#+}} ymm2 = [3,2,7,6]
; AVX512VL-FAST-ALL-NEXT: vpermt2pd %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -545,7 +545,7 @@ define <4 x double> @shuffle_v4f64_1076(<4 x double> %a, <4 x double> %b) {
;
; AVX512VL-FAST-LABEL: shuffle_v4f64_1076:
; AVX512VL-FAST: # %bb.0:
-; AVX512VL-FAST-NEXT: vmovapd {{.*#+}} ymm2 = [1,0,7,6]
+; AVX512VL-FAST-NEXT: vpmovsxbq {{.*#+}} ymm2 = [1,0,7,6]
; AVX512VL-FAST-NEXT: vpermt2pd %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 1, i32 0, i32 7, i32 6>
@@ -569,7 +569,7 @@ define <4 x double> @shuffle_v4f64_0415(<4 x double> %a, <4 x double> %b) {
;
; AVX512VL-LABEL: shuffle_v4f64_0415:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovapd {{.*#+}} ymm2 = [0,4,1,5]
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} ymm2 = [0,4,1,5]
; AVX512VL-NEXT: vpermt2pd %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
@@ -586,7 +586,7 @@ define <4 x double> @shuffle_v4f64_2741(<4 x double> %a, <4 x double> %b) {
;
; AVX512VL-LABEL: shuffle_v4f64_2741:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovapd {{.*#+}} ymm2 = [2,7,4,1]
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} ymm2 = [2,7,4,1]
; AVX512VL-NEXT: vpermt2pd %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 2, i32 7, i32 4, i32 1>
@@ -675,7 +675,7 @@ define <4 x double> @shuffle_v4f64_0456(<4 x double> %a, <4 x double> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v4f64_0456:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovapd {{.*#+}} ymm2 = [4,0,1,2]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbq {{.*#+}} ymm2 = [4,0,1,2]
; AVX512VL-FAST-ALL-NEXT: vpermi2pd %ymm0, %ymm1, %ymm2
; AVX512VL-FAST-ALL-NEXT: vmovapd %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
@@ -762,7 +762,7 @@ define <4 x double> @shuffle_v4f64_0044(<4 x double> %a, <4 x double> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v4f64_0044:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovapd {{.*#+}} ymm2 = [0,0,4,4]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbq {{.*#+}} ymm2 = [0,0,4,4]
; AVX512VL-FAST-ALL-NEXT: vpermt2pd %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
index b815cef63bfd48..bd78dbded0705f 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
@@ -56,7 +56,7 @@ define <8 x float> @shuffle_v8f32_00000010(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_00000010:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,0,0,1,0]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,0,0,1]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -103,7 +103,7 @@ define <8 x float> @shuffle_v8f32_00000200(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_00000200:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,0,2,0,0]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,0,0,0,2,0,0]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -150,7 +150,7 @@ define <8 x float> @shuffle_v8f32_00003000(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_00003000:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,3,0,0,0]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,0,3,0]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -172,11 +172,17 @@ define <8 x float> @shuffle_v8f32_00040000(<8 x float> %a, <8 x float> %b) {
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[2,0],ymm0[4,4],ymm1[6,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8f32_00040000:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,0,4]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8f32_00040000:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,0,4]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8f32_00040000:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,0,0,4]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 0>
ret <8 x float> %shuffle
}
@@ -189,11 +195,17 @@ define <8 x float> @shuffle_v8f32_00500000(<8 x float> %a, <8 x float> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,1,0,4,4,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8f32_00500000:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,5,0]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8f32_00500000:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,5,0]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8f32_00500000:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} xmm1 = [0,5]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x float> %shuffle
}
@@ -206,11 +218,17 @@ define <8 x float> @shuffle_v8f32_06000000(<8 x float> %a, <8 x float> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,0,0,4,4,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8f32_06000000:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovsd {{.*#+}} xmm1 = [0,6,0,0]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8f32_06000000:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovsd {{.*#+}} xmm1 = [0,6,0,0]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8f32_06000000:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,6,0,0]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x float> %shuffle
}
@@ -223,11 +241,17 @@ define <8 x float> @shuffle_v8f32_70000000(<8 x float> %a, <8 x float> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,0,0,0,4,4,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8f32_70000000:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovss {{.*#+}} xmm1 = [7,0,0,0]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8f32_70000000:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovss {{.*#+}} xmm1 = [7,0,0,0]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8f32_70000000:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} xmm1 = [7,0]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x float> %shuffle
}
@@ -249,11 +273,17 @@ define <8 x float> @shuffle_v8f32_00112233(<8 x float> %a, <8 x float> %b) {
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8f32_00112233:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,1,1,2,2,3,3]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8f32_00112233:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,1,1,2,2,3,3]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8f32_00112233:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,1,1,2,2,3,3]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>
ret <8 x float> %shuffle
}
@@ -292,7 +322,7 @@ define <8 x float> @shuffle_v8f32_00001111(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_00001111:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,1,1,1,1]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,0,0,1,1,1,1]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -364,7 +394,7 @@ define <8 x float> @shuffle_v8f32_08084c4c(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-LABEL: shuffle_v8f32_08084c4c:
; AVX512VL-FAST: # %bb.0:
-; AVX512VL-FAST-NEXT: vmovaps {{.*#+}} ymm2 = [0,8,0,8,4,12,4,12]
+; AVX512VL-FAST-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,8,0,8,4,12,4,12]
; AVX512VL-FAST-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 4, i32 12, i32 4, i32 12>
@@ -426,7 +456,7 @@ define <8 x float> @shuffle_v8f32_08192a3b(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-LABEL: shuffle_v8f32_08192a3b:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovaps {{.*#+}} ymm2 = [0,8,1,9,2,10,3,11]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,8,1,9,2,10,3,11]
; AVX512VL-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
@@ -472,7 +502,7 @@ define <8 x float> @shuffle_v8f32_08991abb(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-LABEL: shuffle_v8f32_08991abb:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovaps {{.*#+}} ymm2 = [8,0,1,1,9,2,3,3]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [8,0,1,1,9,2,3,3]
; AVX512VL-NEXT: vpermi2ps %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vmovaps %ymm2, %ymm0
; AVX512VL-NEXT: retq
@@ -503,7 +533,7 @@ define <8 x float> @shuffle_v8f32_091b2d3f(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_091b2d3f:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm2 = [0,9,1,11,2,13,3,15]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,9,1,11,2,13,3,15]
; AVX512VL-FAST-ALL-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -547,7 +577,7 @@ define <8 x float> @shuffle_v8f32_09ab1def(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-LABEL: shuffle_v8f32_09ab1def:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovaps {{.*#+}} ymm2 = [8,1,2,3,9,5,6,7]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [8,1,2,3,9,5,6,7]
; AVX512VL-NEXT: vpermi2ps %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vmovaps %ymm2, %ymm0
; AVX512VL-NEXT: retq
@@ -924,7 +954,7 @@ define <8 x float> @shuffle_v8f32_c348cda0(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-LABEL: shuffle_v8f32_c348cda0:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovaps {{.*#+}} ymm2 = [4,11,12,0,4,5,2,8]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [4,11,12,0,4,5,2,8]
; AVX512VL-NEXT: vpermi2ps %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vmovaps %ymm2, %ymm0
; AVX512VL-NEXT: retq
@@ -972,7 +1002,7 @@ define <8 x float> @shuffle_v8f32_f511235a(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-LABEL: shuffle_v8f32_f511235a:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovaps {{.*#+}} ymm2 = [15,5,1,1,2,3,5,10]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [15,5,1,1,2,3,5,10]
; AVX512VL-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 15, i32 5, i32 1, i32 1, i32 2, i32 3, i32 5, i32 10>
@@ -1108,7 +1138,7 @@ define <8 x float> @shuffle_v8f32_76543210(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_76543210:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [7,6,5,4,3,2,1,0]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [7,6,5,4,3,2,1,0]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -1136,7 +1166,7 @@ define <8 x float> @shuffle_v8f32_3210ba98(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_3210ba98:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm2 = [3,2,1,0,11,10,9,8]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [3,2,1,0,11,10,9,8]
; AVX512VL-FAST-ALL-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -1164,7 +1194,7 @@ define <8 x float> @shuffle_v8f32_3210fedc(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-LABEL: shuffle_v8f32_3210fedc:
; AVX512VL-FAST: # %bb.0:
-; AVX512VL-FAST-NEXT: vmovaps {{.*#+}} ymm2 = [3,2,1,0,15,14,13,12]
+; AVX512VL-FAST-NEXT: vpmovsxbd {{.*#+}} ymm2 = [3,2,1,0,15,14,13,12]
; AVX512VL-FAST-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12>
@@ -1186,7 +1216,7 @@ define <8 x float> @shuffle_v8f32_7654fedc(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_7654fedc:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm2 = [7,6,5,4,15,14,13,12]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [7,6,5,4,15,14,13,12]
; AVX512VL-FAST-ALL-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -1214,7 +1244,7 @@ define <8 x float> @shuffle_v8f32_fedc7654(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_fedc7654:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm2 = [7,6,5,4,15,14,13,12]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [7,6,5,4,15,14,13,12]
; AVX512VL-FAST-ALL-NEXT: vpermi2ps %ymm0, %ymm1, %ymm2
; AVX512VL-FAST-ALL-NEXT: vmovaps %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
@@ -1250,7 +1280,7 @@ define <8 x float> @PR21138(<8 x float> %truc, <8 x float> %tchose) {
;
; AVX512VL-FAST-ALL-LABEL: PR21138:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm2 = [1,3,5,7,9,11,13,15]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [1,3,5,7,9,11,13,15]
; AVX512VL-FAST-ALL-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -1278,7 +1308,7 @@ define <8 x float> @shuffle_v8f32_ba987654(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-LABEL: shuffle_v8f32_ba987654:
; AVX512VL-FAST: # %bb.0:
-; AVX512VL-FAST-NEXT: vmovaps {{.*#+}} ymm2 = [3,2,1,0,15,14,13,12]
+; AVX512VL-FAST-NEXT: vpmovsxbd {{.*#+}} ymm2 = [3,2,1,0,15,14,13,12]
; AVX512VL-FAST-NEXT: vpermi2ps %ymm0, %ymm1, %ymm2
; AVX512VL-FAST-NEXT: vmovaps %ymm2, %ymm0
; AVX512VL-FAST-NEXT: retq
@@ -1301,7 +1331,7 @@ define <8 x float> @shuffle_v8f32_ba983210(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_ba983210:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm2 = [3,2,1,0,11,10,9,8]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [3,2,1,0,11,10,9,8]
; AVX512VL-FAST-ALL-NEXT: vpermi2ps %ymm0, %ymm1, %ymm2
; AVX512VL-FAST-ALL-NEXT: vmovaps %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
@@ -1356,7 +1386,7 @@ define <8 x float> @shuffle_v8f32_084c195d(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_084c195d:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm2 = [0,8,4,12,1,9,5,13]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,8,4,12,1,9,5,13]
; AVX512VL-FAST-ALL-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -1404,7 +1434,7 @@ define <8 x float> @shuffle_v8f32_089abcde(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-LABEL: shuffle_v8f32_089abcde:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovaps {{.*#+}} ymm2 = [8,0,1,2,3,4,5,6]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [8,0,1,2,3,4,5,6]
; AVX512VL-NEXT: vpermi2ps %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vmovaps %ymm2, %ymm0
; AVX512VL-NEXT: retq
@@ -1427,7 +1457,7 @@ define <8 x float> @shuffle_v8f32_0189abcd(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8f32_0189abcd:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovapd {{.*#+}} ymm2 = [4,0,1,2]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbq {{.*#+}} ymm2 = [4,0,1,2]
; AVX512VL-FAST-ALL-NEXT: vpermi2pd %ymm0, %ymm1, %ymm2
; AVX512VL-FAST-ALL-NEXT: vmovapd %ymm2, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
@@ -1459,7 +1489,7 @@ define <8 x float> @shuffle_v8f32_01289abc(<8 x float> %a, <8 x float> %b) {
;
; AVX512VL-LABEL: shuffle_v8f32_01289abc:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovaps {{.*#+}} ymm2 = [8,9,10,0,1,2,3,4]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [8,9,10,0,1,2,3,4]
; AVX512VL-NEXT: vpermi2ps %ymm0, %ymm1, %ymm2
; AVX512VL-NEXT: vmovaps %ymm2, %ymm0
; AVX512VL-NEXT: retq
@@ -1599,7 +1629,7 @@ define <8 x float> @shuffle_mem_v8f32_8BA0CFE4(<8 x float> %a0, ptr %a1) {
;
; AVX512VL-FAST-LABEL: shuffle_mem_v8f32_8BA0CFE4:
; AVX512VL-FAST: # %bb.0:
-; AVX512VL-FAST-NEXT: vmovaps {{.*#+}} ymm1 = [0,3,2,8,4,7,6,12]
+; AVX512VL-FAST-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,3,2,8,4,7,6,12]
; AVX512VL-FAST-NEXT: vpermt2ps (%rdi), %ymm1, %ymm0
; AVX512VL-FAST-NEXT: retq
%1 = load <8 x float>, ptr %a1
@@ -1656,7 +1686,7 @@ define <8 x i32> @shuffle_v8i32_00000010(<8 x i32> %a, <8 x i32> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8i32_00000010:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,0,0,1,0]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,0,0,1]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -1703,7 +1733,7 @@ define <8 x i32> @shuffle_v8i32_00000200(<8 x i32> %a, <8 x i32> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8i32_00000200:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,0,2,0,0]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,0,0,0,2,0,0]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -1750,7 +1780,7 @@ define <8 x i32> @shuffle_v8i32_00003000(<8 x i32> %a, <8 x i32> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8i32_00003000:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,3,0,0,0]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,0,3,0]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -1772,11 +1802,17 @@ define <8 x i32> @shuffle_v8i32_00040000(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[2,0],ymm0[4,4],ymm1[6,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_00040000:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,0,4]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_00040000:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,0,4]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_00040000:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,0,0,4]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %shuffle
}
@@ -1789,11 +1825,17 @@ define <8 x i32> @shuffle_v8i32_00500000(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,1,0,4,4,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_00500000:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,5,0]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_00500000:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,5,0]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_00500000:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} xmm1 = [0,5]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %shuffle
}
@@ -1806,11 +1848,17 @@ define <8 x i32> @shuffle_v8i32_06000000(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,0,0,4,4,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_06000000:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovsd {{.*#+}} xmm1 = [0,6,0,0]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_06000000:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovsd {{.*#+}} xmm1 = [0,6,0,0]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_06000000:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,6,0,0]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %shuffle
}
@@ -1823,11 +1871,17 @@ define <8 x i32> @shuffle_v8i32_70000000(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,0,0,0,4,4,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_70000000:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovss {{.*#+}} xmm1 = [7,0,0,0]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_70000000:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovss {{.*#+}} xmm1 = [7,0,0,0]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_70000000:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} xmm1 = [7,0]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %shuffle
}
@@ -1880,7 +1934,7 @@ define <8 x i32> @shuffle_v8i32_00112233(<8 x i32> %a, <8 x i32> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8i32_00112233:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,1,1,2,2,3,3]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,1,1,2,2,3,3]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -1927,7 +1981,7 @@ define <8 x i32> @shuffle_v8i32_00001111(<8 x i32> %a, <8 x i32> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8i32_00001111:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,1,1,1,1]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,0,0,1,1,1,1]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -2329,11 +2383,17 @@ define <8 x i32> @shuffle_v8i32_00015444(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,0,1,5,4,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_00015444:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,1,5,4,4,4]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_00015444:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,1,5,4,4,4]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_00015444:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,0,1,5,4,4,4]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 5, i32 4, i32 4, i32 4>
ret <8 x i32> %shuffle
}
@@ -2344,11 +2404,17 @@ define <8 x i32> @shuffle_v8i32_00204644(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,0,4,6,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_00204644:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,2,0,4,6,4,4]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_00204644:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,2,0,4,6,4,4]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_00204644:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,2,0,4,6,4,4]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 6, i32 4, i32 4>
ret <8 x i32> %shuffle
}
@@ -2359,11 +2425,17 @@ define <8 x i32> @shuffle_v8i32_03004474(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,3,0,0,4,4,7,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_03004474:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,3,0,0,4,4,7,4]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_03004474:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,3,0,0,4,4,7,4]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_03004474:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,3,0,0,4,4,7,4]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 4, i32 7, i32 4>
ret <8 x i32> %shuffle
}
@@ -2374,11 +2446,17 @@ define <8 x i32> @shuffle_v8i32_10004444(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,0,0,4,4,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_10004444:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,0,0,4,4,4,4]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_10004444:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,0,0,4,4,4,4]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_10004444:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [1,0,0,0,4,4,4,4]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
ret <8 x i32> %shuffle
}
@@ -2389,11 +2467,17 @@ define <8 x i32> @shuffle_v8i32_22006446(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[2,2,0,0,6,4,4,6]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_22006446:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [2,2,0,0,6,4,4,6]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_22006446:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [2,2,0,0,6,4,4,6]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_22006446:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [2,2,0,0,6,4,4,6]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 4, i32 4, i32 6>
ret <8 x i32> %shuffle
}
@@ -2404,11 +2488,17 @@ define <8 x i32> @shuffle_v8i32_33307474(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,3,3,0,7,4,7,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_33307474:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [3,3,3,0,7,4,7,4]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_33307474:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [3,3,3,0,7,4,7,4]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_33307474:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [3,3,3,0,7,4,7,4]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 4, i32 7, i32 4>
ret <8 x i32> %shuffle
}
@@ -2419,11 +2509,17 @@ define <8 x i32> @shuffle_v8i32_32104567(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,4,5,6,7]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_32104567:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [3,2,1,0,4,5,6,7]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_32104567:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [3,2,1,0,4,5,6,7]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_32104567:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [3,2,1,0,4,5,6,7]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
ret <8 x i32> %shuffle
}
@@ -2434,11 +2530,17 @@ define <8 x i32> @shuffle_v8i32_00236744(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,3,6,7,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_00236744:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,2,3,6,7,4,4]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_00236744:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,2,3,6,7,4,4]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_00236744:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,2,3,6,7,4,4]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 6, i32 7, i32 4, i32 4>
ret <8 x i32> %shuffle
}
@@ -2449,11 +2551,17 @@ define <8 x i32> @shuffle_v8i32_00226644(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,2,6,6,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_00226644:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,2,2,6,6,4,4]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_00226644:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,2,2,6,6,4,4]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_00226644:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,2,2,6,6,4,4]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 6, i32 6, i32 4, i32 4>
ret <8 x i32> %shuffle
}
@@ -2464,11 +2572,17 @@ define <8 x i32> @shuffle_v8i32_10324567(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,4,5,6,7]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_10324567:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,3,2,4,5,6,7]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_10324567:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,3,2,4,5,6,7]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_10324567:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [1,0,3,2,4,5,6,7]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 6, i32 7>
ret <8 x i32> %shuffle
}
@@ -2479,11 +2593,17 @@ define <8 x i32> @shuffle_v8i32_11334567(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,1,3,3,4,5,6,7]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_11334567:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [1,1,3,3,4,5,6,7]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_11334567:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [1,1,3,3,4,5,6,7]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_11334567:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [1,1,3,3,4,5,6,7]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i32> %shuffle
}
@@ -2494,11 +2614,17 @@ define <8 x i32> @shuffle_v8i32_01235467(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,1,2,3,5,4,6,7]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_01235467:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,1,2,3,5,4,6,7]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_01235467:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,1,2,3,5,4,6,7]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_01235467:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,1,2,3,5,4,6,7]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 7>
ret <8 x i32> %shuffle
}
@@ -2509,11 +2635,17 @@ define <8 x i32> @shuffle_v8i32_01235466(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,1,2,3,5,4,6,6]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_01235466:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,1,2,3,5,4,6,6]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_01235466:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,1,2,3,5,4,6,6]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_01235466:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,1,2,3,5,4,6,6]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 6>
ret <8 x i32> %shuffle
}
@@ -2524,11 +2656,17 @@ define <8 x i32> @shuffle_v8i32_002u6u44(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,2,u,6,u,4,4]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_002u6u44:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,2,u,6,u,4,4]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_002u6u44:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,2,u,6,u,4,4]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_002u6u44:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,2,0,6,0,4,4]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 poison, i32 6, i32 poison, i32 4, i32 4>
ret <8 x i32> %shuffle
}
@@ -2539,11 +2677,17 @@ define <8 x i32> @shuffle_v8i32_00uu66uu(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,0,u,u,6,6,u,u]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_00uu66uu:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,u,u,6,6,u,u]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_00uu66uu:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,u,u,6,6,u,u]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_00uu66uu:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,0,0,6,6,0,0]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 0, i32 poison, i32 poison, i32 6, i32 6, i32 poison, i32 poison>
ret <8 x i32> %shuffle
}
@@ -2554,11 +2698,17 @@ define <8 x i32> @shuffle_v8i32_103245uu(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,0,3,2,4,5,u,u]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_103245uu:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,3,2,4,5,u,u]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_103245uu:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,3,2,4,5,u,u]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_103245uu:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [1,0,3,2,4,5,0,0]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 poison, i32 poison>
ret <8 x i32> %shuffle
}
@@ -2569,11 +2719,17 @@ define <8 x i32> @shuffle_v8i32_1133uu67(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[1,1,3,3,u,u,6,7]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_1133uu67:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [1,1,3,3,u,u,6,7]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_1133uu67:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [1,1,3,3,u,u,6,7]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_1133uu67:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [1,1,3,3,0,0,6,7]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 poison, i32 poison, i32 6, i32 7>
ret <8 x i32> %shuffle
}
@@ -2584,11 +2740,17 @@ define <8 x i32> @shuffle_v8i32_0uu354uu(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,u,u,3,5,4,u,u]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_0uu354uu:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,u,u,3,5,4,u,u]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_0uu354uu:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [0,u,u,3,5,4,u,u]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_0uu354uu:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,0,3,5,4,0,0]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 poison, i32 poison, i32 3, i32 5, i32 4, i32 poison, i32 poison>
ret <8 x i32> %shuffle
}
@@ -2599,11 +2761,17 @@ define <8 x i32> @shuffle_v8i32_uuu3uu66(<8 x i32> %a, <8 x i32> %b) {
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[u,u,u,3,u,u,6,6]
; AVX1-NEXT: retq
;
-; AVX2OR512VL-LABEL: shuffle_v8i32_uuu3uu66:
-; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [u,u,u,3,u,u,6,6]
-; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; AVX2OR512VL-NEXT: retq
+; AVX2-LABEL: shuffle_v8i32_uuu3uu66:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [u,u,u,3,u,u,6,6]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512VL-LABEL: shuffle_v8i32_uuu3uu66:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,0,0,3,0,0,6,6]
+; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 3, i32 poison, i32 poison, i32 6, i32 6>
ret <8 x i32> %shuffle
}
@@ -2781,7 +2949,7 @@ define <8 x i32> @shuffle_v8i32_76543210(<8 x i32> %a, <8 x i32> %b) {
;
; AVX512VL-FAST-ALL-LABEL: shuffle_v8i32_76543210:
; AVX512VL-FAST-ALL: # %bb.0:
-; AVX512VL-FAST-ALL-NEXT: vmovaps {{.*#+}} ymm1 = [7,6,5,4,3,2,1,0]
+; AVX512VL-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [7,6,5,4,3,2,1,0]
; AVX512VL-FAST-ALL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512VL-FAST-ALL-NEXT: retq
;
@@ -3713,7 +3881,7 @@ define <8 x float> @broadcast_concat_crash(<4 x float> %x, <4 x float> %y, float
; AVX512VL-FAST: # %bb.0: # %entry
; AVX512VL-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512VL-FAST-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,3,3,3]
-; AVX512VL-FAST-NEXT: vmovaps {{.*#+}} xmm1 = [1,4,3,3]
+; AVX512VL-FAST-NEXT: vpmovsxbd {{.*#+}} xmm1 = [1,4,3,3]
; AVX512VL-FAST-NEXT: vpermi2ps %xmm2, %xmm0, %xmm1
; AVX512VL-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512VL-FAST-NEXT: retq
@@ -3847,7 +4015,7 @@ define <8 x float> @lowhalf_v8f32(<8 x float> %x, <8 x float> %y) {
;
; AVX512VL-LABEL: lowhalf_v8f32:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: vmovaps {{.*#+}} xmm2 = [2,14,3,14]
+; AVX512VL-NEXT: vpmovsxbd {{.*#+}} xmm2 = [2,14,3,14]
; AVX512VL-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq
%r = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 2, i32 14, i32 3, i32 14, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
index d3b04878dc06d4..b1efb416014b0e 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
@@ -292,7 +292,7 @@ define <16 x i32> @shuffle_v16i32_01_02_03_16_05_06_07_20_09_10_11_24_13_14_15_2
define <16 x float> @shuffle_v16f32_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01(<16 x float> %a) {
; ALL-LABEL: shuffle_v16f32_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01:
; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} zmm1 = [2,5,u,u,7,u,10,1,0,5,u,4,7,u,10,1]
+; ALL-NEXT: vpmovsxbd {{.*#+}} zmm1 = [2,5,0,0,7,0,10,1,0,5,0,4,7,0,10,1]
; ALL-NEXT: vpermps %zmm0, %zmm1, %zmm0
; ALL-NEXT: retq
%c = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 2, i32 5, i32 poison, i32 poison, i32 7, i32 poison, i32 10, i32 1, i32 0, i32 5, i32 poison, i32 4, i32 7, i32 poison, i32 10, i32 1>
@@ -302,7 +302,7 @@ define <16 x float> @shuffle_v16f32_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01(<
define <16 x i32> @shuffle_v16i32_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01(<16 x i32> %a) {
; ALL-LABEL: shuffle_v16i32_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01:
; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} zmm1 = [2,5,u,u,7,u,10,1,0,5,u,4,7,u,10,1]
+; ALL-NEXT: vpmovsxbd {{.*#+}} zmm1 = [2,5,0,0,7,0,10,1,0,5,0,4,7,0,10,1]
; ALL-NEXT: vpermps %zmm0, %zmm1, %zmm0
; ALL-NEXT: retq
%c = shufflevector <16 x i32> %a, <16 x i32> poison, <16 x i32> <i32 2, i32 5, i32 poison, i32 poison, i32 7, i32 poison, i32 10, i32 1, i32 0, i32 5, i32 poison, i32 4, i32 7, i32 poison, i32 10, i32 1>
@@ -322,7 +322,7 @@ define <16 x i32> @shuffle_v16i32_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_1
define <16 x float> @shuffle_v16f32_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18(<16 x float> %a, <16 x float> %b) {
; ALL-LABEL: shuffle_v16f32_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18:
; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} zmm2 = [15,31,14,22,13,29,4,28,11,27,10,26,9,25,8,24]
+; ALL-NEXT: vpmovsxbd {{.*#+}} zmm2 = [15,31,14,22,13,29,4,28,11,27,10,26,9,25,8,24]
; ALL-NEXT: vpermt2ps %zmm1, %zmm2, %zmm0
; ALL-NEXT: retq
%c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
@@ -339,7 +339,7 @@ define <16 x i32> @shuffle_v16i32_0b_0a_09_08_0f_0e_0d_0c_03_02_01_00_07_06_05_0
;
; FAST-LABEL: shuffle_v16i32_0b_0a_09_08_0f_0e_0d_0c_03_02_01_00_07_06_05_04:
; FAST: # %bb.0:
-; FAST-NEXT: vmovaps {{.*#+}} zmm1 = [11,10,9,8,15,14,13,12,3,2,1,0,7,6,5,4]
+; FAST-NEXT: vpmovsxbd {{.*#+}} zmm1 = [11,10,9,8,15,14,13,12,3,2,1,0,7,6,5,4]
; FAST-NEXT: vpermps %zmm0, %zmm1, %zmm0
; FAST-NEXT: retq
%1 = shufflevector <16 x i32> %a, <16 x i32> poison, <16 x i32> <i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12, i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
@@ -355,7 +355,7 @@ define <16 x float> @shuffle_v16f32_0b_0a_09_08_0f_0e_0d_0c_03_02_01_00_07_06_05
;
; FAST-LABEL: shuffle_v16f32_0b_0a_09_08_0f_0e_0d_0c_03_02_01_00_07_06_05_04:
; FAST: # %bb.0:
-; FAST-NEXT: vmovaps {{.*#+}} zmm1 = [11,10,9,8,15,14,13,12,3,2,1,0,7,6,5,4]
+; FAST-NEXT: vpmovsxbd {{.*#+}} zmm1 = [11,10,9,8,15,14,13,12,3,2,1,0,7,6,5,4]
; FAST-NEXT: vpermps %zmm0, %zmm1, %zmm0
; FAST-NEXT: retq
%1 = shufflevector <16 x float> %a, <16 x float> poison, <16 x i32> <i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12, i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
@@ -365,7 +365,7 @@ define <16 x float> @shuffle_v16f32_0b_0a_09_08_0f_0e_0d_0c_03_02_01_00_07_06_05
define <16 x float> @shuffle_v16f32_load_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18(<16 x float> %a, ptr %b) {
; ALL-LABEL: shuffle_v16f32_load_0f_1f_0e_16_0d_1d_04_1e_0b_1b_0a_1a_09_19_08_18:
; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} zmm1 = [15,31,14,22,13,29,4,28,11,27,10,26,9,25,8,24]
+; ALL-NEXT: vpmovsxbd {{.*#+}} zmm1 = [15,31,14,22,13,29,4,28,11,27,10,26,9,25,8,24]
; ALL-NEXT: vpermt2ps (%rdi), %zmm1, %zmm0
; ALL-NEXT: retq
%c = load <16 x float>, ptr %b
@@ -382,7 +382,7 @@ define <16 x float> @shuffle_v16f32_load_08_11_10_00_12_15_14_04(<16 x float> %a
;
; FAST-LABEL: shuffle_v16f32_load_08_11_10_00_12_15_14_04:
; FAST: # %bb.0:
-; FAST-NEXT: vmovaps {{.*#+}} zmm1 = [0,3,2,16,4,7,6,20,8,11,10,24,12,15,14,28]
+; FAST-NEXT: vpmovsxbd {{.*#+}} zmm1 = [0,3,2,16,4,7,6,20,8,11,10,24,12,15,14,28]
; FAST-NEXT: vpermt2ps (%rdi), %zmm1, %zmm0
; FAST-NEXT: retq
%1 = load <16 x float>, ptr %a1
@@ -421,7 +421,7 @@ define <8 x i32> @test_v16i32_1_3_5_7_9_11_13_15(<16 x i32> %v) {
;
; FAST-LABEL: test_v16i32_1_3_5_7_9_11_13_15:
; FAST: # %bb.0:
-; FAST-NEXT: vmovaps {{.*#+}} ymm1 = [1,3,5,7,9,11,13,15]
+; FAST-NEXT: vpmovsxbd {{.*#+}} ymm1 = [1,3,5,7,9,11,13,15]
; FAST-NEXT: vpermps %zmm0, %zmm1, %zmm0
; FAST-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; FAST-NEXT: retq
@@ -441,7 +441,7 @@ define <4 x i32> @test_v16i32_0_1_2_12 (<16 x i32> %v) {
;
; FAST-LABEL: test_v16i32_0_1_2_12:
; FAST: # %bb.0:
-; FAST-NEXT: vmovaps {{.*#+}} xmm1 = [0,1,2,12]
+; FAST-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,1,2,12]
; FAST-NEXT: vpermps %zmm0, %zmm1, %zmm0
; FAST-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; FAST-NEXT: vzeroupper
@@ -455,7 +455,7 @@ define <4 x i32> @test_v16i32_0_1_2_12 (<16 x i32> %v) {
define <4 x i32> @test_v16i32_0_4_8_12(<16 x i32> %v) {
; ALL-LABEL: test_v16i32_0_4_8_12:
; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} xmm1 = [0,4,8,12]
+; ALL-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,4,8,12]
; ALL-NEXT: vpermps %zmm0, %zmm1, %zmm0
; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; ALL-NEXT: vzeroupper
@@ -478,7 +478,7 @@ define <8 x float> @shuffle_v16f32_extract_256(ptr %RET, ptr %a) {
define <8 x float> @test_v16f32_0_1_2_3_4_6_7_10 (<16 x float> %v) {
; ALL-LABEL: test_v16f32_0_1_2_3_4_6_7_10:
; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} ymm1 = [0,1,2,3,4,6,7,10]
+; ALL-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,1,2,3,4,6,7,10]
; ALL-NEXT: vpermps %zmm0, %zmm1, %zmm0
; ALL-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; ALL-NEXT: retq
@@ -490,7 +490,7 @@ define <8 x float> @test_v16f32_0_1_2_3_4_6_7_10 (<16 x float> %v) {
define <4 x float> @test_v16f32_0_1_3_6 (<16 x float> %v) {
; ALL-LABEL: test_v16f32_0_1_3_6:
; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} xmm1 = [0,1,3,6]
+; ALL-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,1,3,6]
; ALL-NEXT: vpermps %zmm0, %zmm1, %zmm0
; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; ALL-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
index 62327fb2618ce3..4fe50a60b67fab 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
@@ -121,7 +121,7 @@ define <64 x i8> @shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<64 x i8> %a) {
;
; AVX512DQ-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; AVX512DQ: # %bb.0:
-; AVX512DQ-NEXT: vmovss {{.*#+}} xmm1 = [255,0,0,0]
+; AVX512DQ-NEXT: vpmovzxbq {{.*#+}} xmm1 = [255,0]
; AVX512DQ-NEXT: vandps %zmm1, %zmm0, %zmm0
; AVX512DQ-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
index 172ba83d304159..38fdf0b23970a5 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
@@ -44,97 +44,61 @@ define <8 x double> @shuffle_v8f64_44444444_bc(<8 x i64> %a, <8 x i64> %b) {
}
define <8 x double> @shuffle_v8f64_00000010(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00000010:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,1,0]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00000010:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00000010:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,0,0,1,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_00000200(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00000200:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,2,0,0]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00000200:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00000200:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,0,2,0,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 0, i32 0>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_00003000(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00003000:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,3,0,0,0]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00003000:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00003000:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,3,0,0,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_00040000(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00040000:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00040000:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,0,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00040000:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,0,0,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 0>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_00500000(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00500000:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,5,0]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00500000:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,5,0,0,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00500000:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,0,5,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_06000000(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_06000000:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,0,0,0,0,0,0,6,0,0,0,0,0,0,0]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_06000000:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,6,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_06000000:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} xmm1 = [0,6]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x double> %shuffle
}
@@ -142,7 +106,7 @@ define <8 x double> @shuffle_v8f64_06000000(<8 x double> %a, <8 x double> %b) {
define <8 x double> @shuffle_v8f64_70000000(<8 x double> %a, <8 x double> %b) {
; ALL-LABEL: shuffle_v8f64_70000000:
; ALL: # %bb.0:
-; ALL-NEXT: vmovss {{.*#+}} xmm1 = [7,0,0,0]
+; ALL-NEXT: vpmovsxbq {{.*#+}} xmm1 = [7,0]
; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -159,33 +123,21 @@ define <8 x double> @shuffle_v8f64_01014545(<8 x double> %a, <8 x double> %b) {
}
define <8 x double> @shuffle_v8f64_00112233(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00112233:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,1,1,2,2,3,3]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00112233:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,1,0,1,0,2,0,2,0,3,0,3,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00112233:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,1,1,2,2,3,3]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_00001111(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00001111:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,1,1,1,1]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00001111:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,0,0,1,0,1,0,1,0,1,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00001111:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,1,1,1,1]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1>
ret <8 x double> %shuffle
}
@@ -218,171 +170,106 @@ define <8 x double> @shuffle_v8f64_08080808(<8 x double> %a, <8 x double> %b) {
}
define <8 x double> @shuffle_v8f64_08084c4c(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_08084c4c:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [0,8,0,8,4,12,4,12]
-; AVX512F-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_08084c4c:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [0,0,8,0,0,0,8,0,4,0,12,0,4,0,12,0]
-; AVX512F-32-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_08084c4c:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [0,8,0,8,4,12,4,12]
+; ALL-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 8, i32 0, i32 8, i32 4, i32 12, i32 4, i32 12>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_8823cc67(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_8823cc67:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [0,0,10,11,4,4,14,15]
-; AVX512F-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_8823cc67:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [0,0,0,0,10,0,11,0,4,0,4,0,14,0,15,0]
-; AVX512F-32-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-32-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_8823cc67:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [0,0,10,11,4,4,14,15]
+; ALL-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
+; ALL-NEXT: vmovapd %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 8, i32 8, i32 2, i32 3, i32 12, i32 12, i32 6, i32 7>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_9832dc76(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_9832dc76:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [1,0,11,10,5,4,15,14]
-; AVX512F-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_9832dc76:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [1,0,0,0,11,0,10,0,5,0,4,0,15,0,14,0]
-; AVX512F-32-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-32-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_9832dc76:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [1,0,11,10,5,4,15,14]
+; ALL-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
+; ALL-NEXT: vmovapd %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 9, i32 8, i32 3, i32 2, i32 13, i32 12, i32 7, i32 6>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_9810dc54(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_9810dc54:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [1,0,9,8,5,4,13,12]
-; AVX512F-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_9810dc54:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [1,0,0,0,9,0,8,0,5,0,4,0,13,0,12,0]
-; AVX512F-32-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-32-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_9810dc54:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [1,0,9,8,5,4,13,12]
+; ALL-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
+; ALL-NEXT: vmovapd %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 9, i32 8, i32 1, i32 0, i32 13, i32 12, i32 5, i32 4>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_08194c5d(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_08194c5d:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [0,8,1,9,4,12,5,13]
-; AVX512F-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_08194c5d:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [0,0,8,0,1,0,9,0,4,0,12,0,5,0,13,0]
-; AVX512F-32-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_08194c5d:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [0,8,1,9,4,12,5,13]
+; ALL-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_2a3b6e7f(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_2a3b6e7f:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [2,10,3,11,6,14,7,15]
-; AVX512F-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_2a3b6e7f:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [2,0,10,0,3,0,11,0,6,0,14,0,7,0,15,0]
-; AVX512F-32-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_2a3b6e7f:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [2,10,3,11,6,14,7,15]
+; ALL-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_08192a3b(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_08192a3b:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [0,8,1,9,2,10,3,11]
-; AVX512F-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_08192a3b:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [0,0,8,0,1,0,9,0,2,0,10,0,3,0,11,0]
-; AVX512F-32-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_08192a3b:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [0,8,1,9,2,10,3,11]
+; ALL-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_08991abb(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_08991abb:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [8,0,1,1,9,2,3,3]
-; AVX512F-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_08991abb:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [8,0,0,0,1,0,1,0,9,0,2,0,3,0,3,0]
-; AVX512F-32-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-32-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_08991abb:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [8,0,1,1,9,2,3,3]
+; ALL-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
+; ALL-NEXT: vmovapd %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 8, i32 9, i32 9, i32 1, i32 10, i32 11, i32 11>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_091b2d3f(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_091b2d3f:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [0,9,1,11,2,13,3,15]
-; AVX512F-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_091b2d3f:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [0,0,9,0,1,0,11,0,2,0,13,0,3,0,15,0]
-; AVX512F-32-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_091b2d3f:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [0,9,1,11,2,13,3,15]
+; ALL-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 9, i32 1, i32 11, i32 2, i32 13, i32 3, i32 15>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_09ab1def(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_09ab1def:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [8,1,2,3,9,5,6,7]
-; AVX512F-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_09ab1def:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [8,0,1,0,2,0,3,0,9,0,5,0,6,0,7,0]
-; AVX512F-32-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-32-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_09ab1def:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [8,1,2,3,9,5,6,7]
+; ALL-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
+; ALL-NEXT: vmovapd %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 1, i32 13, i32 14, i32 15>
ret <8 x double> %shuffle
}
@@ -505,145 +392,91 @@ define <8 x double> @shuffle_v8f64_10225466(<8 x double> %a, <8 x double> %b) {
}
define <8 x double> @shuffle_v8f64_00015444(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00015444:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,1,5,4,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00015444:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,1,0,5,0,4,0,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00015444:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,1,5,4,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 5, i32 4, i32 4, i32 4>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_00204644(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00204644:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,2,0,4,6,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00204644:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,2,0,0,0,4,0,6,0,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00204644:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,2,0,4,6,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 6, i32 4, i32 4>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_03004474(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_03004474:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,3,0,0,4,4,7,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_03004474:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,3,0,0,0,0,0,4,0,4,0,7,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_03004474:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,3,0,0,4,4,7,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 4, i32 7, i32 4>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_10004444(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_10004444:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [1,0,0,0,4,4,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_10004444:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [1,0,0,0,0,0,0,0,4,0,4,0,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_10004444:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [1,0,0,0,4,4,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_22006446(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_22006446:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [2,2,0,0,6,4,4,6]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_22006446:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [2,0,2,0,0,0,0,0,6,0,4,0,4,0,6,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_22006446:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [2,2,0,0,6,4,4,6]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 4, i32 4, i32 6>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_33307474(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_33307474:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [3,3,3,0,7,4,7,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_33307474:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [3,0,3,0,3,0,0,0,7,0,4,0,7,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_33307474:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [3,3,3,0,7,4,7,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 4, i32 7, i32 4>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_32104567(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_32104567:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [3,2,1,0,4,5,6,7]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_32104567:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [3,0,2,0,1,0,0,0,4,0,5,0,6,0,7,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_32104567:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [3,2,1,0,4,5,6,7]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_00236744(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00236744:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,2,3,6,7,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00236744:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,2,0,3,0,6,0,7,0,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00236744:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,2,3,6,7,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 6, i32 7, i32 4, i32 4>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_00226644(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00226644:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,2,2,6,6,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00226644:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,2,0,2,0,6,0,6,0,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00226644:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,2,2,6,6,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 6, i32 6, i32 4, i32 4>
ret <8 x double> %shuffle
}
@@ -685,33 +518,21 @@ define <8 x double> @shuffle_v8f64_01235466(<8 x double> %a, <8 x double> %b) {
}
define <8 x double> @shuffle_v8f64_002u6u44(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_002u6u44:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,2,u,6,u,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_002u6u44:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,2,0,u,u,6,0,u,u,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_002u6u44:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,2,0,6,0,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 poison, i32 6, i32 poison, i32 4, i32 4>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_00uu66uu(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_00uu66uu:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,u,u,6,6,u,u]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_00uu66uu:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,u,u,u,u,6,0,6,0,u,u,u,u]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_00uu66uu:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,6,6,0,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 poison, i32 poison, i32 6, i32 6, i32 poison, i32 poison>
ret <8 x double> %shuffle
}
@@ -753,35 +574,22 @@ define <8 x double> @shuffle_v8f64_uuu3uu66(<8 x double> %a, <8 x double> %b) {
}
define <8 x double> @shuffle_v8f64_c348cda0(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_c348cda0:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [4,11,12,0,4,5,2,8]
-; AVX512F-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_c348cda0:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [4,0,11,0,12,0,0,0,4,0,5,0,2,0,8,0]
-; AVX512F-32-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; AVX512F-32-NEXT: vmovapd %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_c348cda0:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [4,11,12,0,4,5,2,8]
+; ALL-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
+; ALL-NEXT: vmovapd %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 12, i32 3, i32 4, i32 8, i32 12, i32 13, i32 10, i32 0>
ret <8 x double> %shuffle
}
define <8 x double> @shuffle_v8f64_f511235a(<8 x double> %a, <8 x double> %b) {
-; AVX512F-LABEL: shuffle_v8f64_f511235a:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [15,5,1,1,2,3,5,10]
-; AVX512F-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8f64_f511235a:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovapd {{.*#+}} zmm2 = [15,0,5,0,1,0,1,0,2,0,3,0,5,0,10,0]
-; AVX512F-32-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8f64_f511235a:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm2 = [15,5,1,1,2,3,5,10]
+; ALL-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 15, i32 5, i32 1, i32 1, i32 2, i32 3, i32 5, i32 10>
ret <8 x double> %shuffle
}
@@ -862,97 +670,61 @@ define <8 x i64> @shuffle_v8i64_66666666(<8 x i64> %a, <8 x i64> %b) {
}
define <8 x i64> @shuffle_v8i64_00000010(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00000010:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,1,0]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00000010:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00000010:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,0,0,1,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_00000200(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00000200:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,2,0,0]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00000200:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00000200:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,0,2,0,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 2, i32 0, i32 0>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_00003000(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00003000:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,3,0,0,0]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00003000:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00003000:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,3,0,0,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_00040000(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00040000:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00040000:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,0,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00040000:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,0,0,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 4, i32 0, i32 0, i32 0, i32 0>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_00500000(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00500000:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,5,0]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00500000:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,0,5,0,0,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00500000:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,0,5,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_06000000(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_06000000:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,0,0,0,0,0,0,6,0,0,0,0,0,0,0]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_06000000:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} xmm1 = [0,0,6,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_06000000:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} xmm1 = [0,6]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i64> %shuffle
}
@@ -960,7 +732,7 @@ define <8 x i64> @shuffle_v8i64_06000000(<8 x i64> %a, <8 x i64> %b) {
define <8 x i64> @shuffle_v8i64_70000000(<8 x i64> %a, <8 x i64> %b) {
; ALL-LABEL: shuffle_v8i64_70000000:
; ALL: # %bb.0:
-; ALL-NEXT: vmovss {{.*#+}} xmm1 = [7,0,0,0]
+; ALL-NEXT: vpmovsxbq {{.*#+}} xmm1 = [7,0]
; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -995,33 +767,21 @@ define <8 x i64> @shuffle_v8i64_01014545_mem(ptr %ptr, <8 x i64> %b) {
}
define <8 x i64> @shuffle_v8i64_00112233(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00112233:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,1,1,2,2,3,3]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00112233:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,1,0,1,0,2,0,2,0,3,0,3,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00112233:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,1,1,2,2,3,3]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_00001111(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00001111:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,1,1,1,1]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00001111:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,0,0,1,0,1,0,1,0,1,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00001111:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,1,1,1,1]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1>
ret <8 x i64> %shuffle
}
@@ -1278,305 +1038,191 @@ define <8 x i64> @shuffle_v8i64_10225466(<8 x i64> %a, <8 x i64> %b) {
}
define <8 x i64> @shuffle_v8i64_00015444(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00015444:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,1,5,4,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00015444:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,0,0,1,0,5,0,4,0,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00015444:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,1,5,4,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 1, i32 5, i32 4, i32 4, i32 4>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_00204644(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00204644:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,2,0,4,6,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00204644:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,2,0,0,0,4,0,6,0,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00204644:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,2,0,4,6,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 4, i32 6, i32 4, i32 4>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_03004474(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_03004474:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,3,0,0,4,4,7,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_03004474:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,3,0,0,0,0,0,4,0,4,0,7,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_03004474:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,3,0,0,4,4,7,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 3, i32 0, i32 0, i32 4, i32 4, i32 7, i32 4>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_10004444(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_10004444:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [1,0,0,0,4,4,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_10004444:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [1,0,0,0,0,0,0,0,4,0,4,0,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_10004444:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [1,0,0,0,4,4,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_22006446(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_22006446:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [2,2,0,0,6,4,4,6]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_22006446:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [2,0,2,0,0,0,0,0,6,0,4,0,4,0,6,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_22006446:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [2,2,0,0,6,4,4,6]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 2, i32 0, i32 0, i32 6, i32 4, i32 4, i32 6>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_33307474(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_33307474:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [3,3,3,0,7,4,7,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_33307474:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [3,0,3,0,3,0,0,0,7,0,4,0,7,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_33307474:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [3,3,3,0,7,4,7,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 0, i32 7, i32 4, i32 7, i32 4>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_32104567(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_32104567:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [3,2,1,0,4,5,6,7]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_32104567:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [3,0,2,0,1,0,0,0,4,0,5,0,6,0,7,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_32104567:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [3,2,1,0,4,5,6,7]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 4, i32 5, i32 6, i32 7>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_00236744(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00236744:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,2,3,6,7,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00236744:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,2,0,3,0,6,0,7,0,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00236744:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,2,3,6,7,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 3, i32 6, i32 7, i32 4, i32 4>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_00226644(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00226644:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,2,2,6,6,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00226644:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,2,0,2,0,6,0,6,0,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00226644:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,2,2,6,6,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 6, i32 6, i32 4, i32 4>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_10324567(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_10324567:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [1,0,3,2,4,5,6,7]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_10324567:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [1,0,0,0,3,0,2,0,4,0,5,0,6,0,7,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_10324567:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [1,0,3,2,4,5,6,7]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 6, i32 7>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_11334567(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_11334567:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [1,1,3,3,4,5,6,7]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_11334567:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [1,0,1,0,3,0,3,0,4,0,5,0,6,0,7,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_11334567:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [1,1,3,3,4,5,6,7]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_01235467(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_01235467:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,1,2,3,5,4,6,7]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_01235467:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,1,0,2,0,3,0,5,0,4,0,6,0,7,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_01235467:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,1,2,3,5,4,6,7]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 7>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_01235466(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_01235466:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,1,2,3,5,4,6,6]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_01235466:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,1,0,2,0,3,0,5,0,4,0,6,0,6,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_01235466:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,1,2,3,5,4,6,6]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 6, i32 6>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_002u6u44(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_002u6u44:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,2,u,6,u,4,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_002u6u44:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,2,0,u,u,6,0,u,u,4,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_002u6u44:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,2,0,6,0,4,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 poison, i32 6, i32 poison, i32 4, i32 4>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_00uu66uu(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_00uu66uu:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,u,u,6,6,u,u]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_00uu66uu:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,0,0,u,u,u,u,6,0,6,0,u,u,u,u]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_00uu66uu:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,0,6,6,0,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 poison, i32 poison, i32 6, i32 6, i32 poison, i32 poison>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_103245uu(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_103245uu:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [1,0,3,2,4,5,u,u]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_103245uu:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [1,0,0,0,3,0,2,0,4,0,5,0,u,u,u,u]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_103245uu:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [1,0,3,2,4,5,0,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 4, i32 5, i32 poison, i32 poison>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_1133uu67(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_1133uu67:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [1,1,3,3,u,u,6,7]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_1133uu67:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [1,0,1,0,3,0,3,0,u,u,u,u,6,0,7,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_1133uu67:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [1,1,3,3,0,0,6,7]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 poison, i32 poison, i32 6, i32 7>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_0uu354uu(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_0uu354uu:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [0,u,u,3,5,4,u,u]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_0uu354uu:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,u,u,u,u,3,0,5,0,4,0,u,u,u,u]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_0uu354uu:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,3,5,4,0,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 poison, i32 poison, i32 3, i32 5, i32 4, i32 poison, i32 poison>
ret <8 x i64> %shuffle
}
define <8 x i64> @shuffle_v8i64_uuu3uu66(<8 x i64> %a, <8 x i64> %b) {
-; AVX512F-LABEL: shuffle_v8i64_uuu3uu66:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [u,u,u,3,u,u,6,6]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: shuffle_v8i64_uuu3uu66:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} zmm1 = [u,u,u,u,u,u,3,0,u,u,u,u,6,0,6,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: shuffle_v8i64_uuu3uu66:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,0,3,0,0,6,6]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 3, i32 poison, i32 poison, i32 6, i32 6>
ret <8 x i64> %shuffle
}
@@ -2131,79 +1777,49 @@ define <8 x double> @shuffle_v2f64_v8f64_01010101(<2 x double> %a) {
;FIXME: compressp
define <4 x double> @test_v8f64_2346 (<8 x double> %v) {
-; AVX512F-LABEL: test_v8f64_2346:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} ymm1 = [2,3,4,6]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: test_v8f64_2346:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} ymm1 = [2,0,3,0,4,0,6,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: test_v8f64_2346:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [2,3,4,6]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
+; ALL-NEXT: ret{{[l|q]}}
%res = shufflevector <8 x double> %v, <8 x double> poison, <4 x i32> <i32 2, i32 3, i32 4, i32 6>
ret <4 x double> %res
}
;FIXME: compressp
define <2 x double> @test_v8f64_34 (<8 x double> %v) {
-; AVX512F-LABEL: test_v8f64_34:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} xmm1 = [3,4]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
-; AVX512F-NEXT: vzeroupper
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: test_v8f64_34:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} xmm1 = [3,0,4,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
-; AVX512F-32-NEXT: vzeroupper
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: test_v8f64_34:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} xmm1 = [3,4]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
+; ALL-NEXT: vzeroupper
+; ALL-NEXT: ret{{[l|q]}}
%res = shufflevector <8 x double> %v, <8 x double> poison, <2 x i32> <i32 3, i32 4>
ret <2 x double> %res
}
; FIXME: vpcompress
define <4 x i64> @test_v8i64_1257 (<8 x i64> %v) {
-; AVX512F-LABEL: test_v8i64_1257:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} ymm1 = [1,2,5,7]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: test_v8i64_1257:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,2,0,5,0,7,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: test_v8i64_1257:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [1,2,5,7]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
+; ALL-NEXT: ret{{[l|q]}}
%res = shufflevector <8 x i64> %v, <8 x i64> poison, <4 x i32> <i32 1, i32 2, i32 5, i32 7>
ret <4 x i64> %res
}
define <2 x i64> @test_v8i64_2_5 (<8 x i64> %v) {
-; AVX512F-LABEL: test_v8i64_2_5:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovaps {{.*#+}} xmm1 = [2,5]
-; AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
-; AVX512F-NEXT: vzeroupper
-; AVX512F-NEXT: retq
-;
-; AVX512F-32-LABEL: test_v8i64_2_5:
-; AVX512F-32: # %bb.0:
-; AVX512F-32-NEXT: vmovaps {{.*#+}} xmm1 = [2,0,5,0]
-; AVX512F-32-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
-; AVX512F-32-NEXT: vzeroupper
-; AVX512F-32-NEXT: retl
+; ALL-LABEL: test_v8i64_2_5:
+; ALL: # %bb.0:
+; ALL-NEXT: vpmovsxbq {{.*#+}} xmm1 = [2,5]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
+; ALL-NEXT: vzeroupper
+; ALL-NEXT: ret{{[l|q]}}
%res = shufflevector <8 x i64> %v, <8 x i64> poison, <2 x i32> <i32 2, i32 5>
ret <2 x i64> %res
}
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-avx512.ll b/llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
index 3fd73319e85774..545a9d3e314a2c 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
@@ -38,7 +38,7 @@ define <8 x float> @expand1(<4 x float> %a ) {
; AVX512F-LABEL: expand1:
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; AVX512F-NEXT: vmovaps {{.*#+}} ymm1 = [16,0,18,1,20,2,22,3]
+; AVX512F-NEXT: vpmovsxbd {{.*#+}} ymm1 = [16,0,18,1,20,2,22,3]
; AVX512F-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpermt2ps %zmm2, %zmm1, %zmm0
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
@@ -114,7 +114,7 @@ define <8 x float> @expand5(<4 x float> %a ) {
; AVX512-FAST: # %bb.0:
; AVX512-FAST-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512-FAST-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX512-FAST-NEXT: vmovaps {{.*#+}} ymm2 = [8,0,10,0,12,0,14,0]
+; AVX512-FAST-NEXT: vpmovsxbq {{.*#+}} ymm2 = [8,10,12,14]
; AVX512-FAST-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512-FAST-NEXT: ret{{[l|q]}}
;
@@ -245,7 +245,7 @@ define <16 x float> @expand12(<8 x float> %a) {
; CHECK-LABEL: expand12:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [0,16,2,16,4,16,6,16,0,16,1,16,2,16,3,16]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [0,16,2,16,4,16,6,16,0,16,1,16,2,16,3,16]
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1
; CHECK-NEXT: vmovaps %zmm1, %zmm0
@@ -278,7 +278,7 @@ define <8 x float> @expand14(<4 x float> %a) {
; AVX512F-LABEL: expand14:
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
-; AVX512F-NEXT: vmovaps {{.*#+}} ymm1 = [16,17,0,19,1,21,22,23]
+; AVX512F-NEXT: vpmovsxbd {{.*#+}} ymm1 = [16,17,0,19,1,21,22,23]
; AVX512F-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpermt2ps %zmm2, %zmm1, %zmm0
; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
@@ -300,8 +300,7 @@ define <8 x float> @expand15(<4 x float> %a) {
; AVX512-FAST-LABEL: expand15:
; AVX512-FAST: # %bb.0:
; AVX512-FAST-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
-; AVX512-FAST-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [1,0,0,0,1,0,0,0]
-; AVX512-FAST-NEXT: # ymm1 = mem[0,1,0,1]
+; AVX512-FAST-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,0,1,0]
; AVX512-FAST-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX512-FAST-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1],ymm0[2],mem[3],ymm0[4],mem[5,6,7]
; AVX512-FAST-NEXT: ret{{[l|q]}}
@@ -481,13 +480,13 @@ define <8 x float> @test_masked_permps_v8f32(ptr %vp, <8 x float> %vec2) {
; X86-AVX512-LABEL: test_masked_permps_v8f32:
; X86-AVX512: # %bb.0:
; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-AVX512-NEXT: vmovaps {{.*#+}} ymm1 = [15,14,11,3,15,14,6,7]
+; X86-AVX512-NEXT: vpmovsxbd {{.*#+}} ymm1 = [15,14,11,3,15,14,6,7]
; X86-AVX512-NEXT: vpermt2ps (%eax), %ymm1, %ymm0
; X86-AVX512-NEXT: retl
;
; X64-AVX512-LABEL: test_masked_permps_v8f32:
; X64-AVX512: # %bb.0:
-; X64-AVX512-NEXT: vmovaps {{.*#+}} ymm1 = [15,14,11,3,15,14,6,7]
+; X64-AVX512-NEXT: vpmovsxbd {{.*#+}} ymm1 = [15,14,11,3,15,14,6,7]
; X64-AVX512-NEXT: vpermt2ps (%rdi), %ymm1, %ymm0
; X64-AVX512-NEXT: retq
;
@@ -496,7 +495,7 @@ define <8 x float> @test_masked_permps_v8f32(ptr %vp, <8 x float> %vec2) {
; X86-AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: vmovaps (%eax), %ymm1
-; X86-AVX512F-NEXT: vmovaps {{.*#+}} ymm2 = [23,22,19,3,23,22,6,7]
+; X86-AVX512F-NEXT: vpmovsxbd {{.*#+}} ymm2 = [23,22,19,3,23,22,6,7]
; X86-AVX512F-NEXT: vpermt2ps %zmm1, %zmm2, %zmm0
; X86-AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; X86-AVX512F-NEXT: retl
@@ -505,7 +504,7 @@ define <8 x float> @test_masked_permps_v8f32(ptr %vp, <8 x float> %vec2) {
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; X64-AVX512F-NEXT: vmovaps (%rdi), %ymm1
-; X64-AVX512F-NEXT: vmovaps {{.*#+}} ymm2 = [23,22,19,3,23,22,6,7]
+; X64-AVX512F-NEXT: vpmovsxbd {{.*#+}} ymm2 = [23,22,19,3,23,22,6,7]
; X64-AVX512F-NEXT: vpermt2ps %zmm1, %zmm2, %zmm0
; X64-AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; X64-AVX512F-NEXT: retq
@@ -519,26 +518,26 @@ define <16 x float> @test_masked_permps_v16f32(ptr %vp, <16 x float> %vec2) {
; X86-AVX512-LABEL: test_masked_permps_v16f32:
; X86-AVX512: # %bb.0:
; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [31,29,27,3,30,28,6,7,23,22,19,11,23,13,19,15]
+; X86-AVX512-NEXT: vpmovsxbd {{.*#+}} zmm1 = [31,29,27,3,30,28,6,7,23,22,19,11,23,13,19,15]
; X86-AVX512-NEXT: vpermt2ps (%eax), %zmm1, %zmm0
; X86-AVX512-NEXT: retl
;
; X64-AVX512-LABEL: test_masked_permps_v16f32:
; X64-AVX512: # %bb.0:
-; X64-AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [31,29,27,3,30,28,6,7,23,22,19,11,23,13,19,15]
+; X64-AVX512-NEXT: vpmovsxbd {{.*#+}} zmm1 = [31,29,27,3,30,28,6,7,23,22,19,11,23,13,19,15]
; X64-AVX512-NEXT: vpermt2ps (%rdi), %zmm1, %zmm0
; X64-AVX512-NEXT: retq
;
; X86-AVX512F-LABEL: test_masked_permps_v16f32:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [31,29,27,3,30,28,6,7,23,22,19,11,23,13,19,15]
+; X86-AVX512F-NEXT: vpmovsxbd {{.*#+}} zmm1 = [31,29,27,3,30,28,6,7,23,22,19,11,23,13,19,15]
; X86-AVX512F-NEXT: vpermt2ps (%eax), %zmm1, %zmm0
; X86-AVX512F-NEXT: retl
;
; X64-AVX512F-LABEL: test_masked_permps_v16f32:
; X64-AVX512F: # %bb.0:
-; X64-AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [31,29,27,3,30,28,6,7,23,22,19,11,23,13,19,15]
+; X64-AVX512F-NEXT: vpmovsxbd {{.*#+}} zmm1 = [31,29,27,3,30,28,6,7,23,22,19,11,23,13,19,15]
; X64-AVX512F-NEXT: vpermt2ps (%rdi), %zmm1, %zmm0
; X64-AVX512F-NEXT: retq
%vec = load <16 x float>, ptr %vp
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
index 05071064fc60e1..79602a18693dbe 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
@@ -140,7 +140,7 @@ define <8 x float> @combine_vpermilvar_vperm2f128_zero_8f32(<8 x float> %a0) {
; AVX512-LABEL: combine_vpermilvar_vperm2f128_zero_8f32:
; AVX512: # %bb.0:
; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
-; AVX512-NEXT: vmovaps {{.*#+}} ymm1 = [16,17,18,19,3,2,1,0]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm1 = [16,17,18,19,3,2,1,0]
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512-NEXT: vpermt2ps %zmm2, %zmm1, %zmm0
; AVX512-NEXT: vshufps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
@@ -405,7 +405,7 @@ define void @PR39483() {
; X86-AVX512: # %bb.0: # %entry
; X86-AVX512-NEXT: vmovups 0, %zmm0
; X86-AVX512-NEXT: vmovups 64, %ymm1
-; X86-AVX512-NEXT: vmovaps {{.*#+}} ymm2 = [2,5,8,11,14,17,20,23]
+; X86-AVX512-NEXT: vpmovsxbd {{.*#+}} ymm2 = [2,5,8,11,14,17,20,23]
; X86-AVX512-NEXT: vpermi2ps %zmm1, %zmm0, %zmm2
; X86-AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X86-AVX512-NEXT: vmulps %ymm0, %ymm2, %ymm1
@@ -446,7 +446,7 @@ define void @PR39483() {
; X64-AVX512: # %bb.0: # %entry
; X64-AVX512-NEXT: vmovups 0, %zmm0
; X64-AVX512-NEXT: vmovups 64, %ymm1
-; X64-AVX512-NEXT: vmovaps {{.*#+}} ymm2 = [2,5,8,11,14,17,20,23]
+; X64-AVX512-NEXT: vpmovsxbd {{.*#+}} ymm2 = [2,5,8,11,14,17,20,23]
; X64-AVX512-NEXT: vpermi2ps %zmm1, %zmm0, %zmm2
; X64-AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-AVX512-NEXT: vmulps %ymm0, %ymm2, %ymm1
@@ -521,19 +521,18 @@ define void @PR48908(<4 x double> %v0, <4 x double> %v1, <4 x double> %v2, ptr n
; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm4
-; X86-AVX512-NEXT: vmovapd {{.*#+}} ymm3 = [1,0,2,0,8,0,9,0]
+; X86-AVX512-NEXT: vpmovsxbq {{.*#+}} ymm3 = [1,2,8,9]
; X86-AVX512-NEXT: vpermi2pd %zmm2, %zmm1, %zmm3
-; X86-AVX512-NEXT: vmovapd {{.*#+}} ymm5 = [0,0,10,0,2,0,9,0]
+; X86-AVX512-NEXT: vpmovsxbq {{.*#+}} ymm5 = [0,10,2,9]
; X86-AVX512-NEXT: vperm2f128 {{.*#+}} ymm6 = ymm0[0,1],ymm2[0,1]
; X86-AVX512-NEXT: vpermt2pd %zmm4, %zmm5, %zmm6
; X86-AVX512-NEXT: vmovapd %ymm6, (%edx)
-; X86-AVX512-NEXT: vmovapd {{.*#+}} ymm4 = [0,0,3,0,10,0,1,0]
+; X86-AVX512-NEXT: vpmovsxbq {{.*#+}} ymm4 = [0,3,10,1]
; X86-AVX512-NEXT: vpermi2pd %zmm0, %zmm3, %zmm4
; X86-AVX512-NEXT: vmovapd %ymm4, (%ecx)
-; X86-AVX512-NEXT: vbroadcastf128 {{.*#+}} ymm3 = [3,0,11,0,3,0,11,0]
-; X86-AVX512-NEXT: # ymm3 = mem[0,1,0,1]
+; X86-AVX512-NEXT: vpmovsxbq {{.*#+}} ymm3 = [3,11,0,0]
; X86-AVX512-NEXT: vpermi2pd %zmm1, %zmm0, %zmm3
-; X86-AVX512-NEXT: vmovapd {{.*#+}} ymm0 = [2,0,8,0,9,0,3,0]
+; X86-AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [2,8,9,3]
; X86-AVX512-NEXT: vpermi2pd %zmm3, %zmm2, %zmm0
; X86-AVX512-NEXT: vmovapd %ymm0, (%eax)
; X86-AVX512-NEXT: vzeroupper
@@ -589,18 +588,18 @@ define void @PR48908(<4 x double> %v0, <4 x double> %v1, <4 x double> %v2, ptr n
; X64-AVX512-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
; X64-AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; X64-AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm3
-; X64-AVX512-NEXT: vmovapd {{.*#+}} ymm4 = [1,2,8,9]
+; X64-AVX512-NEXT: vpmovsxbq {{.*#+}} ymm4 = [1,2,8,9]
; X64-AVX512-NEXT: vpermi2pd %zmm2, %zmm1, %zmm4
-; X64-AVX512-NEXT: vmovapd {{.*#+}} ymm5 = [0,10,2,9]
+; X64-AVX512-NEXT: vpmovsxbq {{.*#+}} ymm5 = [0,10,2,9]
; X64-AVX512-NEXT: vperm2f128 {{.*#+}} ymm6 = ymm0[0,1],ymm2[0,1]
; X64-AVX512-NEXT: vpermt2pd %zmm3, %zmm5, %zmm6
; X64-AVX512-NEXT: vmovapd %ymm6, (%rdi)
-; X64-AVX512-NEXT: vmovapd {{.*#+}} ymm3 = [0,3,10,1]
+; X64-AVX512-NEXT: vpmovsxbq {{.*#+}} ymm3 = [0,3,10,1]
; X64-AVX512-NEXT: vpermi2pd %zmm0, %zmm4, %zmm3
; X64-AVX512-NEXT: vmovapd %ymm3, (%rsi)
-; X64-AVX512-NEXT: vmovapd {{.*#+}} xmm3 = [3,11]
+; X64-AVX512-NEXT: vpmovsxbq {{.*#+}} xmm3 = [3,11]
; X64-AVX512-NEXT: vpermi2pd %zmm1, %zmm0, %zmm3
-; X64-AVX512-NEXT: vmovapd {{.*#+}} ymm0 = [2,8,9,3]
+; X64-AVX512-NEXT: vpmovsxbq {{.*#+}} ymm0 = [2,8,9,3]
; X64-AVX512-NEXT: vpermi2pd %zmm3, %zmm2, %zmm0
; X64-AVX512-NEXT: vmovapd %ymm0, (%rdx)
; X64-AVX512-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
index 5488683fa860c3..9e82c84fe5520f 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
@@ -114,11 +114,17 @@ define <4 x i64> @combine_permq_pshufb_as_vmovdqa(<4 x i64> %a0) {
}
define <8 x i32> @combine_as_vpermd(<8 x i32> %a0) {
-; CHECK-LABEL: combine_as_vpermd:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [4,5,4,5,6,7,0,7]
-; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; AVX2-LABEL: combine_as_vpermd:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [4,5,4,5,6,7,0,7]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: ret{{[l|q]}}
+;
+; AVX512-LABEL: combine_as_vpermd:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm1 = [4,5,4,5,6,7,0,7]
+; AVX512-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512-NEXT: ret{{[l|q]}}
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
%2 = tail call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> <i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 7, i32 6>)
%3 = shufflevector <8 x i32> %1, <8 x i32> %2, <8 x i32> <i32 0, i32 8, i32 9, i32 1, i32 15, i32 14, i32 4, i32 3>
@@ -126,11 +132,17 @@ define <8 x i32> @combine_as_vpermd(<8 x i32> %a0) {
}
define <8 x float> @combine_as_vpermps(<8 x float> %a0) {
-; CHECK-LABEL: combine_as_vpermps:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm1 = [6,4,7,5,1,u,4,7]
-; CHECK-NEXT: vpermps %ymm0, %ymm1, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; AVX2-LABEL: combine_as_vpermps:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [6,4,7,5,1,u,4,7]
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: ret{{[l|q]}}
+;
+; AVX512-LABEL: combine_as_vpermps:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm1 = [6,4,7,5,1,0,4,7]
+; AVX512-NEXT: vpermps %ymm0, %ymm1, %ymm0
+; AVX512-NEXT: ret{{[l|q]}}
%1 = shufflevector <8 x float> %a0, <8 x float> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
%2 = tail call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 1, i32 undef, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>)
%3 = shufflevector <8 x float> %1, <8 x float> %2, <8 x i32> <i32 15, i32 0, i32 14, i32 1, i32 8, i32 9, i32 4, i32 3>
@@ -764,10 +776,15 @@ define <32 x i8> @combine_pshufb_pshufb_or_pshufb(<32 x i8> %a0) {
}
define <8 x i32> @constant_fold_permd() {
-; CHECK-LABEL: constant_fold_permd:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [5,7,3,2,8,2,6,1]
-; CHECK-NEXT: ret{{[l|q]}}
+; AVX2-LABEL: constant_fold_permd:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [5,7,3,2,8,2,6,1]
+; AVX2-NEXT: ret{{[l|q]}}
+;
+; AVX512-LABEL: constant_fold_permd:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [5,7,3,2,8,2,6,1]
+; AVX512-NEXT: ret{{[l|q]}}
%1 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>, <8 x i32> <i32 4, i32 6, i32 2, i32 1, i32 7, i32 1, i32 5, i32 0>)
ret <8 x i32> %1
}
@@ -843,7 +860,7 @@ define internal fastcc <8 x float> @PR34577(<8 x float> %inp0, <8 x float> %inp1
; AVX512-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[1,1,1,1]
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX512-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm0[4,5],ymm2[6,7]
-; AVX512-NEXT: vmovaps {{.*#+}} ymm0 = [23,18,7,2,20,u,3,2]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm0 = [23,18,7,2,20,0,3,2]
; AVX512-NEXT: vpermi2ps %zmm2, %zmm1, %zmm0
; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; AVX512-NEXT: ret{{[l|q]}}
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
index 29806cd25fe3f4..d64d2d8a638c69 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
@@ -33,42 +33,42 @@ define <8 x double> @combine_permvar_8f64_identity(<8 x double> %x0, <8 x double
define <8 x double> @combine_permvar_8f64_identity_mask(<8 x double> %x0, <8 x double> %x1, i8 %m) {
; X86-AVX512F-LABEL: combine_permvar_8f64_identity_mask:
; X86-AVX512F: # %bb.0:
-; X86-AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0]
+; X86-AVX512F-NEXT: vpmovsxbq {{.*#+}} zmm2 = [7,6,5,4,3,2,1,0]
; X86-AVX512F-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: kmovw %eax, %k1
; X86-AVX512F-NEXT: vpermpd %zmm0, %zmm2, %zmm1 {%k1}
-; X86-AVX512F-NEXT: vmovapd {{.*#+}} zmm0 = [7,0,14,0,5,0,12,0,3,0,10,0,1,0,8,0]
+; X86-AVX512F-NEXT: vpmovsxbq {{.*#+}} zmm0 = [7,14,5,12,3,10,1,8]
; X86-AVX512F-NEXT: vpermpd %zmm1, %zmm0, %zmm1 {%k1}
; X86-AVX512F-NEXT: vmovapd %zmm1, %zmm0
; X86-AVX512F-NEXT: retl
;
; X86-AVX512BW-LABEL: combine_permvar_8f64_identity_mask:
; X86-AVX512BW: # %bb.0:
-; X86-AVX512BW-NEXT: vmovapd {{.*#+}} zmm2 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0]
+; X86-AVX512BW-NEXT: vpmovsxbq {{.*#+}} zmm2 = [7,6,5,4,3,2,1,0]
; X86-AVX512BW-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: kmovd %eax, %k1
; X86-AVX512BW-NEXT: vpermpd %zmm0, %zmm2, %zmm1 {%k1}
-; X86-AVX512BW-NEXT: vmovapd {{.*#+}} zmm0 = [7,0,14,0,5,0,12,0,3,0,10,0,1,0,8,0]
+; X86-AVX512BW-NEXT: vpmovsxbq {{.*#+}} zmm0 = [7,14,5,12,3,10,1,8]
; X86-AVX512BW-NEXT: vpermpd %zmm1, %zmm0, %zmm1 {%k1}
; X86-AVX512BW-NEXT: vmovapd %zmm1, %zmm0
; X86-AVX512BW-NEXT: retl
;
; X64-AVX512F-LABEL: combine_permvar_8f64_identity_mask:
; X64-AVX512F: # %bb.0:
-; X64-AVX512F-NEXT: vmovapd {{.*#+}} zmm2 = [7,6,5,4,3,2,1,0]
+; X64-AVX512F-NEXT: vpmovsxbq {{.*#+}} zmm2 = [7,6,5,4,3,2,1,0]
; X64-AVX512F-NEXT: kmovw %edi, %k1
; X64-AVX512F-NEXT: vpermpd %zmm0, %zmm2, %zmm1 {%k1}
-; X64-AVX512F-NEXT: vmovapd {{.*#+}} zmm0 = [7,14,5,12,3,10,1,8]
+; X64-AVX512F-NEXT: vpmovsxbq {{.*#+}} zmm0 = [7,14,5,12,3,10,1,8]
; X64-AVX512F-NEXT: vpermpd %zmm1, %zmm0, %zmm1 {%k1}
; X64-AVX512F-NEXT: vmovapd %zmm1, %zmm0
; X64-AVX512F-NEXT: retq
;
; X64-AVX512BW-LABEL: combine_permvar_8f64_identity_mask:
; X64-AVX512BW: # %bb.0:
-; X64-AVX512BW-NEXT: vmovapd {{.*#+}} zmm2 = [7,6,5,4,3,2,1,0]
+; X64-AVX512BW-NEXT: vpmovsxbq {{.*#+}} zmm2 = [7,6,5,4,3,2,1,0]
; X64-AVX512BW-NEXT: kmovd %edi, %k1
; X64-AVX512BW-NEXT: vpermpd %zmm0, %zmm2, %zmm1 {%k1}
-; X64-AVX512BW-NEXT: vmovapd {{.*#+}} zmm0 = [7,14,5,12,3,10,1,8]
+; X64-AVX512BW-NEXT: vpmovsxbq {{.*#+}} zmm0 = [7,14,5,12,3,10,1,8]
; X64-AVX512BW-NEXT: vpermpd %zmm1, %zmm0, %zmm1 {%k1}
; X64-AVX512BW-NEXT: vmovapd %zmm1, %zmm0
; X64-AVX512BW-NEXT: retq
@@ -151,7 +151,7 @@ define <8 x double> @combine_vpermt2var_8f64_identity(<8 x double> %x0, <8 x dou
define <8 x double> @combine_vpermt2var_8f64_identity_mask(<8 x double> %x0, <8 x double> %x1, i8 %m) {
; X86-AVX512F-LABEL: combine_vpermt2var_8f64_identity_mask:
; X86-AVX512F: # %bb.0:
-; X86-AVX512F-NEXT: vmovapd {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0]
+; X86-AVX512F-NEXT: vpmovsxbq {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; X86-AVX512F-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: kmovw %eax, %k1
; X86-AVX512F-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
@@ -160,7 +160,7 @@ define <8 x double> @combine_vpermt2var_8f64_identity_mask(<8 x double> %x0, <8
;
; X86-AVX512BW-LABEL: combine_vpermt2var_8f64_identity_mask:
; X86-AVX512BW: # %bb.0:
-; X86-AVX512BW-NEXT: vmovapd {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0]
+; X86-AVX512BW-NEXT: vpmovsxbq {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; X86-AVX512BW-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: kmovd %eax, %k1
; X86-AVX512BW-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
@@ -169,7 +169,7 @@ define <8 x double> @combine_vpermt2var_8f64_identity_mask(<8 x double> %x0, <8
;
; X64-AVX512F-LABEL: combine_vpermt2var_8f64_identity_mask:
; X64-AVX512F: # %bb.0:
-; X64-AVX512F-NEXT: vmovapd {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
+; X64-AVX512F-NEXT: vpmovsxbq {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; X64-AVX512F-NEXT: kmovw %edi, %k1
; X64-AVX512F-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: vpermpd %zmm0, %zmm1, %zmm0 {%k1} {z}
@@ -177,7 +177,7 @@ define <8 x double> @combine_vpermt2var_8f64_identity_mask(<8 x double> %x0, <8
;
; X64-AVX512BW-LABEL: combine_vpermt2var_8f64_identity_mask:
; X64-AVX512BW: # %bb.0:
-; X64-AVX512BW-NEXT: vmovapd {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
+; X64-AVX512BW-NEXT: vpmovsxbq {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; X64-AVX512BW-NEXT: kmovd %edi, %k1
; X64-AVX512BW-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: vpermpd %zmm0, %zmm1, %zmm0 {%k1} {z}
@@ -298,7 +298,7 @@ define <16 x float> @combine_vpermt2var_16f32_identity(<16 x float> %x0, <16 x f
define <16 x float> @combine_vpermt2var_16f32_identity_mask(<16 x float> %x0, <16 x float> %x1, i16 %m) {
; X86-LABEL: combine_vpermt2var_16f32_identity_mask:
; X86: # %bb.0:
-; X86-NEXT: vmovaps {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
+; X86-NEXT: vpmovsxbd {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
; X86-NEXT: vpermt2ps %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-NEXT: vpermps %zmm0, %zmm1, %zmm0 {%k1} {z}
@@ -306,7 +306,7 @@ define <16 x float> @combine_vpermt2var_16f32_identity_mask(<16 x float> %x0, <1
;
; X64-AVX512F-LABEL: combine_vpermt2var_16f32_identity_mask:
; X64-AVX512F: # %bb.0:
-; X64-AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
+; X64-AVX512F-NEXT: vpmovsxbd {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X64-AVX512F-NEXT: kmovw %edi, %k1
; X64-AVX512F-NEXT: vpermt2ps %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: vpermps %zmm0, %zmm1, %zmm0 {%k1} {z}
@@ -314,7 +314,7 @@ define <16 x float> @combine_vpermt2var_16f32_identity_mask(<16 x float> %x0, <1
;
; X64-AVX512BW-LABEL: combine_vpermt2var_16f32_identity_mask:
; X64-AVX512BW: # %bb.0:
-; X64-AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
+; X64-AVX512BW-NEXT: vpmovsxbd {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X64-AVX512BW-NEXT: kmovd %edi, %k1
; X64-AVX512BW-NEXT: vpermt2ps %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: vpermps %zmm0, %zmm1, %zmm0 {%k1} {z}
@@ -790,34 +790,22 @@ define <16 x i32> @vpermt2var_vpermi2var_16i32_as_unpckldq(<16 x i32> %a0, <16 x
}
define <8 x double> @combine_vpermi2var_8f64_as_vpermpd(<8 x double> %x0, <8 x double> %x1) {
-; X86-LABEL: combine_vpermi2var_8f64_as_vpermpd:
-; X86: # %bb.0:
-; X86-NEXT: vmovaps {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0]
-; X86-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; X86-NEXT: retl
-;
-; X64-LABEL: combine_vpermi2var_8f64_as_vpermpd:
-; X64: # %bb.0:
-; X64-NEXT: vmovaps {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
-; X64-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; X64-NEXT: retq
+; CHECK-LABEL: combine_vpermi2var_8f64_as_vpermpd:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
+; CHECK-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res0 = call <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double> %x0, <8 x i64> <i64 3, i64 2, i64 1, i64 0, i64 7, i64 6, i64 5, i64 4>, <8 x double> %x1, i8 -1)
%res1 = call <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double> %res0, <8 x i64> <i64 12, i64 5, i64 14, i64 7, i64 8, i64 1, i64 10, i64 3>, <8 x double> %res0, i8 -1)
ret <8 x double> %res1
}
define <8 x i64> @combine_vpermt2var_8i64_as_vpermq(<8 x i64> %x0, <8 x i64> %x1) {
-; X86-LABEL: combine_vpermt2var_8i64_as_vpermq:
-; X86: # %bb.0:
-; X86-NEXT: vmovaps {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0]
-; X86-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; X86-NEXT: retl
-;
-; X64-LABEL: combine_vpermt2var_8i64_as_vpermq:
-; X64: # %bb.0:
-; X64-NEXT: vmovaps {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
-; X64-NEXT: vpermpd %zmm0, %zmm1, %zmm0
-; X64-NEXT: retq
+; CHECK-LABEL: combine_vpermt2var_8i64_as_vpermq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
+; CHECK-NEXT: vpermpd %zmm0, %zmm1, %zmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res0 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> <i64 3, i64 2, i64 1, i64 0, i64 7, i64 6, i64 5, i64 4>, <8 x i64> %x0, <8 x i64> %x1, i8 -1)
%res1 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> <i64 12, i64 5, i64 14, i64 7, i64 8, i64 1, i64 10, i64 3>, <8 x i64> %res0, <8 x i64> %res0, i8 -1)
ret <8 x i64> %res1
@@ -826,7 +814,7 @@ define <8 x i64> @combine_vpermt2var_8i64_as_vpermq(<8 x i64> %x0, <8 x i64> %x1
define <16 x float> @combine_vpermi2var_16f32_as_vpermps(<16 x float> %x0, <16 x float> %x1) {
; CHECK-LABEL: combine_vpermi2var_16f32_as_vpermps:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [7,7,5,5,3,3,1,1,15,15,13,13,11,11,9,9]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm1 = [7,7,5,5,3,3,1,1,15,15,13,13,11,11,9,9]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: ret{{[l|q]}}
%res0 = call <16 x float> @llvm.x86.avx512.mask.vpermi2var.ps.512(<16 x float> %x0, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>, <16 x float> %x1, i16 -1)
@@ -837,7 +825,7 @@ define <16 x float> @combine_vpermi2var_16f32_as_vpermps(<16 x float> %x0, <16 x
define <16 x i32> @combine_vpermt2var_16i32_as_vpermd(<16 x i32> %x0, <16 x i32> %x1) {
; CHECK-LABEL: combine_vpermt2var_16i32_as_vpermd:
; CHECK: # %bb.0:
-; CHECK-NEXT: vmovaps {{.*#+}} zmm1 = [7,7,5,5,3,3,1,1,15,15,13,13,11,11,9,9]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm1 = [7,7,5,5,3,3,1,1,15,15,13,13,11,11,9,9]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: ret{{[l|q]}}
%res0 = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>, <16 x i32> %x0, <16 x i32> %x1, i16 -1)
@@ -864,19 +852,12 @@ define <16 x i32> @combine_vpermt2var_16i32_as_vpsllq(<16 x i32> %x0) {
}
define <8 x double> @combine_vpermi2var_vpermt2var_8f64_as_vperm2(<8 x double> %x0, <8 x double> %x1) {
-; X86-LABEL: combine_vpermi2var_vpermt2var_8f64_as_vperm2:
-; X86: # %bb.0:
-; X86-NEXT: vmovapd {{.*#+}} zmm2 = [4,0,14,0,3,0,12,0,7,0,8,0,0,0,15,0]
-; X86-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; X86-NEXT: vmovapd %zmm2, %zmm0
-; X86-NEXT: retl
-;
-; X64-LABEL: combine_vpermi2var_vpermt2var_8f64_as_vperm2:
-; X64: # %bb.0:
-; X64-NEXT: vmovapd {{.*#+}} zmm2 = [4,14,3,12,7,8,0,15]
-; X64-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
-; X64-NEXT: vmovapd %zmm2, %zmm0
-; X64-NEXT: retq
+; CHECK-LABEL: combine_vpermi2var_vpermt2var_8f64_as_vperm2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm2 = [4,14,3,12,7,8,0,15]
+; CHECK-NEXT: vpermi2pd %zmm0, %zmm1, %zmm2
+; CHECK-NEXT: vmovapd %zmm2, %zmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res0 = call <8 x double> @llvm.x86.avx512.mask.vpermi2var.pd.512(<8 x double> %x0, <8 x i64> <i64 15, i64 0, i64 8, i64 7, i64 12, i64 6, i64 11, i64 4>, <8 x double> %x1, i8 -1)
%res1 = call <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64> <i64 12, i64 5, i64 14, i64 7, i64 8, i64 1, i64 10, i64 3>, <8 x double> %res0, <8 x double> %res0, i8 -1)
ret <8 x double> %res1
@@ -915,19 +896,12 @@ define <16 x i32> @combine_vpermi2var_vpermt2var_16i32_as_vpermd(<16 x i32> %x0,
}
define <8 x double> @combine_vpermi2var_vpermvar_8f64_as_vperm2_zero(<8 x double> %x0) {
-; X86-LABEL: combine_vpermi2var_vpermvar_8f64_as_vperm2_zero:
-; X86: # %bb.0:
-; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; X86-NEXT: vmovapd {{.*#+}} zmm2 = [8,0,3,0,10,0,11,0,1,0,7,0,14,0,5,0]
-; X86-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; X86-NEXT: retl
-;
-; X64-LABEL: combine_vpermi2var_vpermvar_8f64_as_vperm2_zero:
-; X64: # %bb.0:
-; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; X64-NEXT: vmovapd {{.*#+}} zmm2 = [8,3,10,11,1,7,14,5]
-; X64-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
-; X64-NEXT: retq
+; CHECK-LABEL: combine_vpermi2var_vpermvar_8f64_as_vperm2_zero:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vpmovsxbq {{.*#+}} zmm2 = [8,3,10,11,1,7,14,5]
+; CHECK-NEXT: vpermt2pd %zmm1, %zmm2, %zmm0
+; CHECK-NEXT: ret{{[l|q]}}
%res0 = shufflevector <8 x double> %x0, <8 x double> zeroinitializer, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
%1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %res0, <8 x i64> <i64 3, i64 2, i64 1, i64 7, i64 0, i64 6, i64 5, i64 4>)
ret <8 x double> %1
@@ -937,7 +911,7 @@ define <16 x float> @combine_vpermi2var_vpermvar_16f32_as_vperm2_zero(<16 x floa
; CHECK-LABEL: combine_vpermi2var_vpermvar_16f32_as_vperm2_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [0,13,1,12,4,9,22,12,4,25,26,9,5,29,30,8]
+; CHECK-NEXT: vpmovsxbd {{.*#+}} zmm2 = [0,13,1,12,4,9,22,12,4,25,26,9,5,29,30,8]
; CHECK-NEXT: vpermt2ps %zmm1, %zmm2, %zmm0
; CHECK-NEXT: ret{{[l|q]}}
%res0 = shufflevector <16 x float> %x0, <16 x float> zeroinitializer, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 4, i32 20, i32 5, i32 21, i32 8, i32 24, i32 9, i32 25, i32 12, i32 28, i32 13, i32 29>
diff --git a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
index 882b816370478e..ad73bb6886b9f4 100644
--- a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
@@ -1765,29 +1765,44 @@ define <2 x i64> @foldv2i64() nounwind {
; SSE-NEXT: movss {{.*#+}} xmm0 = [8,0,0,0]
; SSE-NEXT: retq
;
-; AVX-LABEL: foldv2i64:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
-; AVX-NEXT: retq
+; AVX1-LABEL: foldv2i64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv2i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; AVX2-NEXT: retq
+;
+; AVX512CDVL-LABEL: foldv2i64:
+; AVX512CDVL: # %bb.0:
+; AVX512CDVL-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
+; AVX512CDVL-NEXT: retq
+;
+; AVX512CD-LABEL: foldv2i64:
+; AVX512CD: # %bb.0:
+; AVX512CD-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
+; AVX512CD-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: foldv2i64:
; AVX512VPOPCNTDQ: # %bb.0:
-; AVX512VPOPCNTDQ-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; AVX512VPOPCNTDQ-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: foldv2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
-; AVX512VPOPCNTDQVL-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; AVX512VPOPCNTDQVL-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv2i64:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; BITALG_NOVLX-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv2i64:
; BITALG: # %bb.0:
-; BITALG-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; BITALG-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
; BITALG-NEXT: retq
;
; X86-SSE-LABEL: foldv2i64:
@@ -1804,29 +1819,44 @@ define <2 x i64> @foldv2i64u() nounwind {
; SSE-NEXT: movss {{.*#+}} xmm0 = [8,0,0,0]
; SSE-NEXT: retq
;
-; AVX-LABEL: foldv2i64u:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
-; AVX-NEXT: retq
+; AVX1-LABEL: foldv2i64u:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv2i64u:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; AVX2-NEXT: retq
+;
+; AVX512CDVL-LABEL: foldv2i64u:
+; AVX512CDVL: # %bb.0:
+; AVX512CDVL-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
+; AVX512CDVL-NEXT: retq
+;
+; AVX512CD-LABEL: foldv2i64u:
+; AVX512CD: # %bb.0:
+; AVX512CD-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
+; AVX512CD-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: foldv2i64u:
; AVX512VPOPCNTDQ: # %bb.0:
-; AVX512VPOPCNTDQ-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; AVX512VPOPCNTDQ-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: foldv2i64u:
; AVX512VPOPCNTDQVL: # %bb.0:
-; AVX512VPOPCNTDQVL-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; AVX512VPOPCNTDQVL-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv2i64u:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; BITALG_NOVLX-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv2i64u:
; BITALG: # %bb.0:
-; BITALG-NEXT: vmovss {{.*#+}} xmm0 = [8,0,0,0]
+; BITALG-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,0]
; BITALG-NEXT: retq
;
; X86-SSE-LABEL: foldv2i64u:
@@ -1843,29 +1873,44 @@ define <4 x i32> @foldv4i32() nounwind {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,32,0]
; SSE-NEXT: retq
;
-; AVX-LABEL: foldv4i32:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
-; AVX-NEXT: retq
+; AVX1-LABEL: foldv4i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv4i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; AVX2-NEXT: retq
+;
+; AVX512CDVL-LABEL: foldv4i32:
+; AVX512CDVL: # %bb.0:
+; AVX512CDVL-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
+; AVX512CDVL-NEXT: retq
+;
+; AVX512CD-LABEL: foldv4i32:
+; AVX512CD: # %bb.0:
+; AVX512CD-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
+; AVX512CD-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: foldv4i32:
; AVX512VPOPCNTDQ: # %bb.0:
-; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; AVX512VPOPCNTDQ-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: foldv4i32:
; AVX512VPOPCNTDQVL: # %bb.0:
-; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; AVX512VPOPCNTDQVL-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv4i32:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; BITALG_NOVLX-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv4i32:
; BITALG: # %bb.0:
-; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; BITALG-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
; BITALG-NEXT: retq
;
; X86-SSE-LABEL: foldv4i32:
@@ -1882,29 +1927,44 @@ define <4 x i32> @foldv4i32u() nounwind {
; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,32,0]
; SSE-NEXT: retq
;
-; AVX-LABEL: foldv4i32u:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
-; AVX-NEXT: retq
+; AVX1-LABEL: foldv4i32u:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv4i32u:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; AVX2-NEXT: retq
+;
+; AVX512CDVL-LABEL: foldv4i32u:
+; AVX512CDVL: # %bb.0:
+; AVX512CDVL-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
+; AVX512CDVL-NEXT: retq
+;
+; AVX512CD-LABEL: foldv4i32u:
+; AVX512CD: # %bb.0:
+; AVX512CD-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
+; AVX512CD-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: foldv4i32u:
; AVX512VPOPCNTDQ: # %bb.0:
-; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; AVX512VPOPCNTDQ-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: foldv4i32u:
; AVX512VPOPCNTDQVL: # %bb.0:
-; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; AVX512VPOPCNTDQVL-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv4i32u:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; BITALG_NOVLX-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv4i32u:
; BITALG: # %bb.0:
-; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0]
+; BITALG-NEXT: vpmovsxbq {{.*#+}} xmm0 = [8,32]
; BITALG-NEXT: retq
;
; X86-SSE-LABEL: foldv4i32u:
diff --git a/llvm/test/CodeGen/X86/vector-tzcnt-256.ll b/llvm/test/CodeGen/X86/vector-tzcnt-256.ll
index 5bcdf0e22a5aec..3c35f7b7fb7518 100644
--- a/llvm/test/CodeGen/X86/vector-tzcnt-256.ll
+++ b/llvm/test/CodeGen/X86/vector-tzcnt-256.ll
@@ -1140,19 +1140,44 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind {
}
define <4 x i64> @foldv4i64() nounwind {
-; AVX-LABEL: foldv4i64:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0]
-; AVX-NEXT: retq
+; AVX1-LABEL: foldv4i64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv4i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0]
+; AVX2-NEXT: retq
+;
+; AVX512CDVL-LABEL: foldv4i64:
+; AVX512CDVL: # %bb.0:
+; AVX512CDVL-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
+; AVX512CDVL-NEXT: retq
+;
+; AVX512CD-LABEL: foldv4i64:
+; AVX512CD: # %bb.0:
+; AVX512CD-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
+; AVX512CD-NEXT: retq
+;
+; AVX512VPOPCNTDQ-LABEL: foldv4i64:
+; AVX512VPOPCNTDQ: # %bb.0:
+; AVX512VPOPCNTDQ-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
+; AVX512VPOPCNTDQ-NEXT: retq
+;
+; AVX512VPOPCNTDQVL-LABEL: foldv4i64:
+; AVX512VPOPCNTDQVL: # %bb.0:
+; AVX512VPOPCNTDQVL-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
+; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv4i64:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0]
+; BITALG_NOVLX-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv4i64:
; BITALG: # %bb.0:
-; BITALG-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0]
+; BITALG-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
; BITALG-NEXT: retq
;
; X86-AVX-LABEL: foldv4i64:
@@ -1164,19 +1189,44 @@ define <4 x i64> @foldv4i64() nounwind {
}
define <4 x i64> @foldv4i64u() nounwind {
-; AVX-LABEL: foldv4i64u:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0]
-; AVX-NEXT: retq
+; AVX1-LABEL: foldv4i64u:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv4i64u:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0]
+; AVX2-NEXT: retq
+;
+; AVX512CDVL-LABEL: foldv4i64u:
+; AVX512CDVL: # %bb.0:
+; AVX512CDVL-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
+; AVX512CDVL-NEXT: retq
+;
+; AVX512CD-LABEL: foldv4i64u:
+; AVX512CD: # %bb.0:
+; AVX512CD-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
+; AVX512CD-NEXT: retq
+;
+; AVX512VPOPCNTDQ-LABEL: foldv4i64u:
+; AVX512VPOPCNTDQ: # %bb.0:
+; AVX512VPOPCNTDQ-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
+; AVX512VPOPCNTDQ-NEXT: retq
+;
+; AVX512VPOPCNTDQVL-LABEL: foldv4i64u:
+; AVX512VPOPCNTDQVL: # %bb.0:
+; AVX512VPOPCNTDQVL-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
+; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv4i64u:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0]
+; BITALG_NOVLX-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv4i64u:
; BITALG: # %bb.0:
-; BITALG-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,64,0]
+; BITALG-NEXT: vpmovsxbq {{.*#+}} ymm0 = [8,0,64,0]
; BITALG-NEXT: retq
;
; X86-AVX-LABEL: foldv4i64u:
@@ -1188,19 +1238,99 @@ define <4 x i64> @foldv4i64u() nounwind {
}
define <8 x i32> @foldv8i32() nounwind {
-; ALL-LABEL: foldv8i32:
-; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
-; ALL-NEXT: ret{{[l|q]}}
+; AVX1-LABEL: foldv8i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv8i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX2-NEXT: retq
+;
+; AVX512CDVL-LABEL: foldv8i32:
+; AVX512CDVL: # %bb.0:
+; AVX512CDVL-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX512CDVL-NEXT: retq
+;
+; AVX512CD-LABEL: foldv8i32:
+; AVX512CD: # %bb.0:
+; AVX512CD-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX512CD-NEXT: retq
+;
+; AVX512VPOPCNTDQ-LABEL: foldv8i32:
+; AVX512VPOPCNTDQ: # %bb.0:
+; AVX512VPOPCNTDQ-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX512VPOPCNTDQ-NEXT: retq
+;
+; AVX512VPOPCNTDQVL-LABEL: foldv8i32:
+; AVX512VPOPCNTDQVL: # %bb.0:
+; AVX512VPOPCNTDQVL-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX512VPOPCNTDQVL-NEXT: retq
+;
+; BITALG_NOVLX-LABEL: foldv8i32:
+; BITALG_NOVLX: # %bb.0:
+; BITALG_NOVLX-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; BITALG_NOVLX-NEXT: retq
+;
+; BITALG-LABEL: foldv8i32:
+; BITALG: # %bb.0:
+; BITALG-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; BITALG-NEXT: retq
+;
+; X86-AVX-LABEL: foldv8i32:
+; X86-AVX: # %bb.0:
+; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; X86-AVX-NEXT: retl
%out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> <i32 256, i32 -1, i32 0, i32 255, i32 -65536, i32 7, i32 24, i32 88>, i1 0)
ret <8 x i32> %out
}
define <8 x i32> @foldv8i32u() nounwind {
-; ALL-LABEL: foldv8i32u:
-; ALL: # %bb.0:
-; ALL-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
-; ALL-NEXT: ret{{[l|q]}}
+; AVX1-LABEL: foldv8i32u:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: foldv8i32u:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX2-NEXT: retq
+;
+; AVX512CDVL-LABEL: foldv8i32u:
+; AVX512CDVL: # %bb.0:
+; AVX512CDVL-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX512CDVL-NEXT: retq
+;
+; AVX512CD-LABEL: foldv8i32u:
+; AVX512CD: # %bb.0:
+; AVX512CD-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX512CD-NEXT: retq
+;
+; AVX512VPOPCNTDQ-LABEL: foldv8i32u:
+; AVX512VPOPCNTDQ: # %bb.0:
+; AVX512VPOPCNTDQ-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX512VPOPCNTDQ-NEXT: retq
+;
+; AVX512VPOPCNTDQVL-LABEL: foldv8i32u:
+; AVX512VPOPCNTDQVL: # %bb.0:
+; AVX512VPOPCNTDQVL-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; AVX512VPOPCNTDQVL-NEXT: retq
+;
+; BITALG_NOVLX-LABEL: foldv8i32u:
+; BITALG_NOVLX: # %bb.0:
+; BITALG_NOVLX-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; BITALG_NOVLX-NEXT: retq
+;
+; BITALG-LABEL: foldv8i32u:
+; BITALG: # %bb.0:
+; BITALG-NEXT: vpmovsxbd {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; BITALG-NEXT: retq
+;
+; X86-AVX-LABEL: foldv8i32u:
+; X86-AVX: # %bb.0:
+; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [8,0,32,0,16,0,3,3]
+; X86-AVX-NEXT: retl
%out = call <8 x i32> @llvm.cttz.v8i32(<8 x i32> <i32 256, i32 -1, i32 0, i32 255, i32 -65536, i32 7, i32 24, i32 88>, i1 -1)
ret <8 x i32> %out
}
@@ -1245,3 +1375,5 @@ declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>, i1)
declare <8 x i32> @llvm.cttz.v8i32(<8 x i32>, i1)
declare <16 x i16> @llvm.cttz.v16i16(<16 x i16>, i1)
declare <32 x i8> @llvm.cttz.v32i8(<32 x i8>, i1)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/CodeGen/X86/vselect-avx.ll b/llvm/test/CodeGen/X86/vselect-avx.ll
index 06474559644b03..d07b7b574eba75 100644
--- a/llvm/test/CodeGen/X86/vselect-avx.ll
+++ b/llvm/test/CodeGen/X86/vselect-avx.ll
@@ -373,7 +373,7 @@ define void @vselect_concat_splat() {
; AVX512: ## %bb.0: ## %entry
; AVX512-NEXT: vmovups (%rax), %ymm0
; AVX512-NEXT: vmovups (%rax), %xmm1
-; AVX512-NEXT: vmovaps {{.*#+}} ymm2 = [0,3,6,9,1,4,7,10]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,3,6,9,1,4,7,10]
; AVX512-NEXT: vmovaps %ymm2, %ymm3
; AVX512-NEXT: vpermi2ps %ymm1, %ymm0, %ymm3
; AVX512-NEXT: vmovups 32, %xmm4
diff --git a/llvm/test/CodeGen/X86/widen_fadd.ll b/llvm/test/CodeGen/X86/widen_fadd.ll
index be249ddc0cca3a..e2c36393da2f6f 100644
--- a/llvm/test/CodeGen/X86/widen_fadd.ll
+++ b/llvm/test/CodeGen/X86/widen_fadd.ll
@@ -303,7 +303,7 @@ define void @widen_fadd_v2f32_v16f32(ptr %a0, ptr %b0, ptr %c0) {
; AVX512VL-NEXT: vpermi2pd %zmm6, %zmm4, %zmm5
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm3, %zmm2, %zmm2
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm0
-; AVX512VL-NEXT: vmovapd {{.*#+}} ymm1 = [0,2,4,6]
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,2,4,6]
; AVX512VL-NEXT: vpermi2pd %ymm2, %ymm0, %ymm1
; AVX512VL-NEXT: vinsertf64x4 $0, %ymm1, %zmm5, %zmm0
; AVX512VL-NEXT: vmovupd %zmm0, (%rdx)
diff --git a/llvm/test/CodeGen/X86/widen_fdiv.ll b/llvm/test/CodeGen/X86/widen_fdiv.ll
index e4c9278478a5b5..4e5695500fbffd 100644
--- a/llvm/test/CodeGen/X86/widen_fdiv.ll
+++ b/llvm/test/CodeGen/X86/widen_fdiv.ll
@@ -251,7 +251,7 @@ define void @widen_fdiv_v2f32_v16f32(ptr %a0, ptr %b0, ptr %c0) {
; AVX512VL-NEXT: vpermi2pd %zmm6, %zmm4, %zmm5
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm3, %zmm2, %zmm2
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm0
-; AVX512VL-NEXT: vmovapd {{.*#+}} ymm1 = [0,2,4,6]
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,2,4,6]
; AVX512VL-NEXT: vpermi2pd %ymm2, %ymm0, %ymm1
; AVX512VL-NEXT: vinsertf64x4 $0, %ymm1, %zmm5, %zmm0
; AVX512VL-NEXT: vmovupd %zmm0, (%rdx)
diff --git a/llvm/test/CodeGen/X86/widen_fmul.ll b/llvm/test/CodeGen/X86/widen_fmul.ll
index 9aa9d63e7fcbd0..fc099e7c689698 100644
--- a/llvm/test/CodeGen/X86/widen_fmul.ll
+++ b/llvm/test/CodeGen/X86/widen_fmul.ll
@@ -303,7 +303,7 @@ define void @widen_fmul_v2f32_v16f32(ptr %a0, ptr %b0, ptr %c0) {
; AVX512VL-NEXT: vpermi2pd %zmm6, %zmm4, %zmm5
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm3, %zmm2, %zmm2
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm0
-; AVX512VL-NEXT: vmovapd {{.*#+}} ymm1 = [0,2,4,6]
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,2,4,6]
; AVX512VL-NEXT: vpermi2pd %ymm2, %ymm0, %ymm1
; AVX512VL-NEXT: vinsertf64x4 $0, %ymm1, %zmm5, %zmm0
; AVX512VL-NEXT: vmovupd %zmm0, (%rdx)
diff --git a/llvm/test/CodeGen/X86/widen_fsub.ll b/llvm/test/CodeGen/X86/widen_fsub.ll
index 60e54ab71abcff..3256d5c6f5e3fb 100644
--- a/llvm/test/CodeGen/X86/widen_fsub.ll
+++ b/llvm/test/CodeGen/X86/widen_fsub.ll
@@ -303,7 +303,7 @@ define void @widen_fsub_v2f32_v16f32(ptr %a0, ptr %b0, ptr %c0) {
; AVX512VL-NEXT: vpermi2pd %zmm6, %zmm4, %zmm5
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm3, %zmm2, %zmm2
; AVX512VL-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm0
-; AVX512VL-NEXT: vmovapd {{.*#+}} ymm1 = [0,2,4,6]
+; AVX512VL-NEXT: vpmovsxbq {{.*#+}} ymm1 = [0,2,4,6]
; AVX512VL-NEXT: vpermi2pd %ymm2, %ymm0, %ymm1
; AVX512VL-NEXT: vinsertf64x4 $0, %ymm1, %zmm5, %zmm0
; AVX512VL-NEXT: vmovupd %zmm0, (%rdx)
diff --git a/llvm/test/CodeGen/X86/x86-interleaved-access.ll b/llvm/test/CodeGen/X86/x86-interleaved-access.ll
index cf2b1117581ddd..3d49edbb7bd8d2 100644
--- a/llvm/test/CodeGen/X86/x86-interleaved-access.ll
+++ b/llvm/test/CodeGen/X86/x86-interleaved-access.ll
@@ -1652,7 +1652,7 @@ define void @splat2_v4f64_load_store(ptr %s, ptr %d) nounwind {
; AVX512-LABEL: splat2_v4f64_load_store:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovups (%rdi), %ymm0
-; AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,1,1,2,2,3,3]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,1,1,2,2,3,3]
; AVX512-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512-NEXT: vmovups %zmm0, (%rsi)
; AVX512-NEXT: vzeroupper
@@ -1689,7 +1689,7 @@ define void @splat2_v4i64_load_store(ptr %s, ptr %d) nounwind {
; AVX512-LABEL: splat2_v4i64_load_store:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovups (%rdi), %ymm0
-; AVX512-NEXT: vmovaps {{.*#+}} zmm1 = [0,0,1,1,2,2,3,3]
+; AVX512-NEXT: vpmovsxbq {{.*#+}} zmm1 = [0,0,1,1,2,2,3,3]
; AVX512-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; AVX512-NEXT: vmovups %zmm0, (%rsi)
; AVX512-NEXT: vzeroupper
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