[llvm] b622cc6 - [X86] LowerCTPOP - check if the operand is a constant when collecting KnownBits

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2025-01-11T13:41:50Z
New Revision: b622cc67d0af9326b9e4f1f91d8be790c57dd86c

URL: https://github.com/llvm/llvm-project/commit/b622cc67d0af9326b9e4f1f91d8be790c57dd86c
DIFF: https://github.com/llvm/llvm-project/commit/b622cc67d0af9326b9e4f1f91d8be790c57dd86c.diff

LOG: [X86] LowerCTPOP - check if the operand is a constant when collecting KnownBits

Under certain circumstances, lowering of other instructions can result in computeKnownBits being able to detect a constant that it couldn't previously.

Fixes #122580

Added: 
    llvm/test/CodeGen/X86/pr122580.ll

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index fbfcfc700ed62d..596139d0845701 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -32172,6 +32172,8 @@ static SDValue LowerCTPOP(SDValue N, const X86Subtarget &Subtarget,
     // allowing us to shift the active bits down if necessary to fit into the
     // special cases below.
     KnownBits Known = DAG.computeKnownBits(Op);
+    if (Known.isConstant())
+      return DAG.getConstant(Known.getConstant().popcount(), DL, VT);
     unsigned LZ = Known.countMinLeadingZeros();
     unsigned TZ = Known.countMinTrailingZeros();
     assert((LZ + TZ) < Known.getBitWidth() && "Illegal shifted mask");

diff  --git a/llvm/test/CodeGen/X86/pr122580.ll b/llvm/test/CodeGen/X86/pr122580.ll
new file mode 100644
index 00000000000000..509729416cf573
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr122580.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
+
+ at g_180 = external global i8
+ at g_1032 = external global [2 x i32]
+
+define i32 @PR122580(ptr %0) {
+; CHECK-LABEL: PR122580:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq g_180 at GOTPCREL(%rip), %rax
+; CHECK-NEXT:    cmpb $0, (%rax)
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    movl $878456583, %ecx # imm = 0x345C2F07
+; CHECK-NEXT:    cmovnel %eax, %ecx
+; CHECK-NEXT:    movq g_1032 at GOTPCREL(%rip), %rax
+; CHECK-NEXT:    movl $0, (%rax)
+; CHECK-NEXT:    movl %ecx, (%rdi)
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    retq
+entry:
+  %.b577 = load i1, ptr @g_180, align 4
+  %1 = select i1 %.b577, i32 1, i32 878456582
+  store i32 0, ptr @g_1032, align 4
+  %.b576 = load i1, ptr @g_180, align 4
+  %2 = select i1 %.b576, i32 1, i32 878456582
+  %or542.1.i = or i32 %2, %1
+  store i32 0, ptr @g_1032, align 4
+  %.b575 = load i1, ptr @g_180, align 4
+  %3 = select i1 %.b575, i32 1, i32 878456582
+  %or542.2.i = or i32 %3, %or542.1.i
+  %or542.3.i = or i32 %or542.2.i, 1
+  store i32 %or542.3.i, ptr %0, align 4
+  %4 = load i32, ptr %0, align 4
+  %div.i1796.i = sdiv i32 %4, 1096912269
+  %5 = tail call i32 @llvm.ctpop.i32(i32 %div.i1796.i)
+  ret i32 %5
+}