[clang] [llvm] [RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (PR #122256)

[Sam Elliott via llvm-commits]

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@@ -313,6 +313,7 @@ enum OperandType : unsigned {
   OPERAND_UIMM8_LSB000,
   OPERAND_UIMM8_GE32,
   OPERAND_UIMM9_LSB000,
+  OPERAND_UIMM10,
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lenary wrote:

Please can you add `CASE_OPERAND_UIMM(10)` to the right place in `RISCVInstrInfo::verifyInstruction`?

https://github.com/llvm/llvm-project/pull/122256