[llvm] [SelectionDAG] Add an ISD node for vector.extract.last.active (PR #118810)

[Graham Hunter via llvm-commits]

huntergr-arm wrote:

Splitting out just the passthru handling didn't change the generated code much, but splitting out the extract from finding the last active index seems to have removed the regressions (and possibly improved RV64 codegen? slli+srli -> andi). DAG combining to lastb/clastb is very easy with this approach, so I think this is close to what we want.

There's still a slight problem with `getBitWidthForCttzElements` though, at least for RV32 -- I have it hardcoded to cap at 32bits to avoid needing to expand the result into 2 32b scalar registers. I'll investigate whether I can remove the type promotion (needed for AArch64 atm) from the vector op expansion code in the meantime.

https://github.com/llvm/llvm-project/pull/118810