[llvm] [DAG] Allow AssertZExt to scalarize. (PR #122463)

[David Green via llvm-commits]

https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/122463

With range and undef metadata on a call we can have vector AssertZExt generated on a target with no vector operations. The AssertZExt needs to scalarize to a normal `AssertZext tin, ValueType`. I have added AssertSext too, although I do not have a test case.

Fixes #110374

>From 012b53b198cb8ce91bbe20f5870ca0138ad642c0 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Fri, 10 Jan 2025 14:34:54 +0000
Subject: [PATCH] [DAG] Allow AssertZExt to scalarize.

With range and undef metadata on a call we can have vector AssertZExt generated
on a target with no vector operations. The AssertZExt needs to scalarize to a
normal `AssertZext tin, ValueType`. I have added AssertSext too, although I do
not have a test case.
---
 .../SelectionDAG/LegalizeVectorTypes.cpp      |  6 +++-
 .../test/CodeGen/ARM/scalarize-assert-zext.ll | 28 +++++++++++++++++++
 2 files changed, 33 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/ARM/scalarize-assert-zext.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 780eba16c9c498..137d662c79ca41 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -58,7 +58,11 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::BUILD_VECTOR:      R = ScalarizeVecRes_BUILD_VECTOR(N); break;
   case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
   case ISD::FP_ROUND:          R = ScalarizeVecRes_FP_ROUND(N); break;
-  case ISD::FPOWI:             R = ScalarizeVecRes_ExpOp(N); break;
+  case ISD::AssertZext:
+  case ISD::AssertSext:
+  case ISD::FPOWI:
+    R = ScalarizeVecRes_ExpOp(N);
+    break;
   case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
   case ISD::LOAD:           R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
   case ISD::SCALAR_TO_VECTOR:  R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
diff --git a/llvm/test/CodeGen/ARM/scalarize-assert-zext.ll b/llvm/test/CodeGen/ARM/scalarize-assert-zext.ll
new file mode 100644
index 00000000000000..47b49b5316ebfc
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/scalarize-assert-zext.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=armv7-unknown-linux-musleabihf -mattr=-neon %s -o - | FileCheck %s
+
+declare fastcc noundef range(i16 0, 256) <4 x i16> @other()
+
+define void @test(ptr %0) #0 {
+; CHECK-LABEL: test:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    bl other
+; CHECK-NEXT:    uxth r3, r3
+; CHECK-NEXT:    uxth r2, r2
+; CHECK-NEXT:    uxth r1, r1
+; CHECK-NEXT:    uxth r0, r0
+; CHECK-NEXT:    strb r3, [r4, #3]
+; CHECK-NEXT:    strb r2, [r4, #2]
+; CHECK-NEXT:    strb r1, [r4, #1]
+; CHECK-NEXT:    strb r0, [r4]
+; CHECK-NEXT:    pop {r4, pc}
+entry:
+  %call33.i70 = call fastcc <4 x i16> @other()
+  %conv.i.i.i71 = trunc <4 x i16> %call33.i70 to <4 x i8>
+  store <4 x i8> %conv.i.i.i71, ptr %0, align 1
+  ret void
+}
+