[llvm] [RISCV] Fold vector shift of sext/zext to widening multiply (PR #121563)

[Piotr Fusik via llvm-commits]

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@@ -432,19 +432,35 @@ define <8 x i32> @vwsll_vx_i8_v8i32_zext(<8 x i16> %a, i8 %b) {
 }
 
 define <8 x i32> @vwsll_vi_v8i32(<8 x i16> %a) {
-; CHECK-LABEL: vwsll_vi_v8i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT:    vzext.vf2 v10, v8
-; CHECK-NEXT:    vsll.vi v8, v10, 2
-; CHECK-NEXT:    ret
+; RV32-LABEL: vwsll_vi_v8i32:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT:    vzext.vf2 v10, v8
+; RV32-NEXT:    vsll.vi v8, v10, 2
+; RV32-NEXT:    ret
 ;
-; CHECK-ZVBB-LABEL: vwsll_vi_v8i32:
-; CHECK-ZVBB:       # %bb.0:
-; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-ZVBB-NEXT:    vwsll.vi v10, v8, 2
-; CHECK-ZVBB-NEXT:    vmv2r.v v8, v10
-; CHECK-ZVBB-NEXT:    ret
+; RV64-LABEL: vwsll_vi_v8i32:
+; RV64:       # %bb.0:
+; RV64-NEXT:    li a0, 4
+; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; RV64-NEXT:    vwmulu.vx v10, v8, a0
+; RV64-NEXT:    vmv2r.v v8, v10
+; RV64-NEXT:    ret
+;
+; CHECK-ZVBB-RV32-LABEL: vwsll_vi_v8i32:
+; CHECK-ZVBB-RV32:       # %bb.0:
+; CHECK-ZVBB-RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-ZVBB-RV32-NEXT:    vwsll.vi v10, v8, 2
+; CHECK-ZVBB-RV32-NEXT:    vmv2r.v v8, v10
+; CHECK-ZVBB-RV32-NEXT:    ret
+;
+; CHECK-ZVBB-RV64-LABEL: vwsll_vi_v8i32:
+; CHECK-ZVBB-RV64:       # %bb.0:
+; CHECK-ZVBB-RV64-NEXT:    li a0, 4
+; CHECK-ZVBB-RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-ZVBB-RV64-NEXT:    vwmulu.vx v10, v8, a0
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pfusik wrote:

Fixed by delaying this transform.

https://github.com/llvm/llvm-project/pull/121563