[llvm] [AMDGPU] Fix unreachable reg bit width (PR #122107)

[via llvm-commits]

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@@ -0,0 +1,12 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=early-machinelicm -run-pass=postmisched -o - %s | FileCheck %s
+---
+name:            test_xnull_256
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Shoreshen wrote:

Hi, to trigger the unreachable during postmisched pass it has to be MIMG instruction, but I cannot find MIMG instruction uses SReg_128_XNULL

I also tried to find other places that may use the bit width function:

1. used in selectCOPY
2. used in foldOperand, but for immediate only
3. used in canInsertSelect test if it is ok to insert a select instruction
4. used in buildSpillLoadStore but it seems like the target registers are all caller/callee saved regs
5. used in printRegularOperand but only for Op.isDFPImm()
6. used in getRegOperandSize, which is used in validateMIMGAddrSize and validateMIMGDataSize

The only possibility is getRegSplitParts, but it is used by many function, I need help on this since I do not familiar with the fucntion.

https://github.com/llvm/llvm-project/pull/122107