[llvm] [BOLT][AArch64] Add isPush & isPop (PR #120713)
Alexey Moksyakov via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 10 04:23:23 PST 2025
https://github.com/yavtuk updated https://github.com/llvm/llvm-project/pull/120713
>From 5b614ec037d198cc2cc488b9997f3ab543ae2eff Mon Sep 17 00:00:00 2001
From: Moksyakov Alexey <yavtuk at yandex.ru>
Date: Fri, 20 Dec 2024 09:18:41 +0000
Subject: [PATCH 1/2] [BOLT][Aarch64] Add isPush & isPop checking
This functionality is needed for inliner pass and also
for correct dyno stats.
---
.../Target/AArch64/AArch64MCPlusBuilder.cpp | 467 ++++++++++++++++--
1 file changed, 425 insertions(+), 42 deletions(-)
diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
index 679c9774c767f7..994ec58ea83de0 100644
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -133,6 +133,16 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
public:
using MCPlusBuilder::MCPlusBuilder;
+ MCPhysReg getFramePointer() const override { return AArch64::FP; }
+
+ bool isPush(const MCInst &Inst) const override {
+ return isStoreToStack(Inst);
+ };
+
+ bool isPop(const MCInst &Inst) const override {
+ return isLoadFromStack(Inst);
+ };
+
bool equals(const MCTargetExpr &A, const MCTargetExpr &B,
CompFuncTy Comp) const override {
const auto &AArch64ExprA = cast<AArch64MCExpr>(A);
@@ -214,59 +224,210 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}
bool isLDRB(const MCInst &Inst) const {
- return (Inst.getOpcode() == AArch64::LDRBBpost ||
- Inst.getOpcode() == AArch64::LDRBBpre ||
- Inst.getOpcode() == AArch64::LDRBBroW ||
- Inst.getOpcode() == AArch64::LDRBBroX ||
- Inst.getOpcode() == AArch64::LDRBBui ||
- Inst.getOpcode() == AArch64::LDRSBWpost ||
- Inst.getOpcode() == AArch64::LDRSBWpre ||
- Inst.getOpcode() == AArch64::LDRSBWroW ||
- Inst.getOpcode() == AArch64::LDRSBWroX ||
- Inst.getOpcode() == AArch64::LDRSBWui ||
- Inst.getOpcode() == AArch64::LDRSBXpost ||
- Inst.getOpcode() == AArch64::LDRSBXpre ||
- Inst.getOpcode() == AArch64::LDRSBXroW ||
- Inst.getOpcode() == AArch64::LDRSBXroX ||
- Inst.getOpcode() == AArch64::LDRSBXui);
+ const unsigned opcode = Inst.getOpcode();
+ bool isLoad = false;
+ switch (opcode) {
+ case AArch64::LDRBpost:
+ case AArch64::LDRBBpost:
+ case AArch64::LDRBBpre:
+ case AArch64::LDRBBroW:
+ case AArch64::LDRBroW:
+ case AArch64::LDRBroX:
+ case AArch64::LDRBBroX:
+ case AArch64::LDRBBui:
+ case AArch64::LDRBui:
+ case AArch64::LDRBpre:
+ case AArch64::LDRSBWpost:
+ case AArch64::LDRSBWpre:
+ case AArch64::LDRSBWroW:
+ case AArch64::LDRSBWroX:
+ case AArch64::LDRSBWui:
+ case AArch64::LDRSBXpost:
+ case AArch64::LDRSBXpre:
+ case AArch64::LDRSBXroW:
+ case AArch64::LDRSBXroX:
+ case AArch64::LDRSBXui:
+ case AArch64::LDURBi:
+ case AArch64::LDURBBi:
+ case AArch64::LDURSBWi:
+ case AArch64::LDURSBXi:
+ case AArch64::LDTRBi:
+ case AArch64::LDTRSBWi:
+ case AArch64::LDTRSBXi:
+ isLoad = true;
+ break;
+ default:
+ break;
+ }
+ return isLoad;
}
bool isLDRH(const MCInst &Inst) const {
- return (Inst.getOpcode() == AArch64::LDRHHpost ||
- Inst.getOpcode() == AArch64::LDRHHpre ||
- Inst.getOpcode() == AArch64::LDRHHroW ||
- Inst.getOpcode() == AArch64::LDRHHroX ||
- Inst.getOpcode() == AArch64::LDRHHui ||
- Inst.getOpcode() == AArch64::LDRSHWpost ||
- Inst.getOpcode() == AArch64::LDRSHWpre ||
- Inst.getOpcode() == AArch64::LDRSHWroW ||
- Inst.getOpcode() == AArch64::LDRSHWroX ||
- Inst.getOpcode() == AArch64::LDRSHWui ||
- Inst.getOpcode() == AArch64::LDRSHXpost ||
- Inst.getOpcode() == AArch64::LDRSHXpre ||
- Inst.getOpcode() == AArch64::LDRSHXroW ||
- Inst.getOpcode() == AArch64::LDRSHXroX ||
- Inst.getOpcode() == AArch64::LDRSHXui);
+ const unsigned opcode = Inst.getOpcode();
+ bool isLoad = false;
+ switch (opcode) {
+ case AArch64::LDRHpost:
+ case AArch64::LDRHHpost:
+ case AArch64::LDRHHpre:
+ case AArch64::LDRHroW:
+ case AArch64::LDRHHroW:
+ case AArch64::LDRHroX:
+ case AArch64::LDRHHroX:
+ case AArch64::LDRHHui:
+ case AArch64::LDRHui:
+ case AArch64::LDRHpre:
+ case AArch64::LDRSHWpost:
+ case AArch64::LDRSHWpre:
+ case AArch64::LDRSHWroW:
+ case AArch64::LDRSHWroX:
+ case AArch64::LDRSHWui:
+ case AArch64::LDRSHXpost:
+ case AArch64::LDRSHXpre:
+ case AArch64::LDRSHXroW:
+ case AArch64::LDRSHXroX:
+ case AArch64::LDRSHXui:
+ case AArch64::LDURHi:
+ case AArch64::LDURHHi:
+ case AArch64::LDURSHWi:
+ case AArch64::LDURSHXi:
+ case AArch64::LDTRHi:
+ case AArch64::LDTRSHWi:
+ case AArch64::LDTRSHXi:
+ isLoad = true;
+ break;
+ default:
+ break;
+ }
+ return isLoad;
}
bool isLDRW(const MCInst &Inst) const {
- return (Inst.getOpcode() == AArch64::LDRWpost ||
- Inst.getOpcode() == AArch64::LDRWpre ||
- Inst.getOpcode() == AArch64::LDRWroW ||
- Inst.getOpcode() == AArch64::LDRWroX ||
- Inst.getOpcode() == AArch64::LDRWui);
+ const unsigned opcode = Inst.getOpcode();
+ bool isLoad = false;
+ switch (opcode) {
+ case AArch64::LDRWpost:
+ case AArch64::LDRWpre:
+ case AArch64::LDRWroW:
+ case AArch64::LDRWroX:
+ case AArch64::LDRWui:
+ case AArch64::LDURWi:
+ case AArch64::LDRSWpost:
+ case AArch64::LDRSWpre:
+ case AArch64::LDRSWroW:
+ case AArch64::LDRSWroX:
+ case AArch64::LDRSWui:
+ case AArch64::LDURSWi:
+ case AArch64::LDTRWi:
+ case AArch64::LDTRSWi:
+ case AArch64::LDPWi:
+ case AArch64::LDPWpost:
+ case AArch64::LDPWpre:
+ case AArch64::LDPSWi:
+ case AArch64::LDPSWpost:
+ case AArch64::LDPSWpre:
+ case AArch64::LDNPWi:
+ isLoad = true;
+ default:
+ break;
+ }
+ return isLoad;
}
bool isLDRX(const MCInst &Inst) const {
- return (Inst.getOpcode() == AArch64::LDRXpost ||
- Inst.getOpcode() == AArch64::LDRXpre ||
- Inst.getOpcode() == AArch64::LDRXroW ||
- Inst.getOpcode() == AArch64::LDRXroX ||
- Inst.getOpcode() == AArch64::LDRXui);
+ const unsigned opcode = Inst.getOpcode();
+ bool isLoad = false;
+ switch (opcode) {
+ case AArch64::LDRXpost:
+ case AArch64::LDRXpre:
+ case AArch64::LDRXroW:
+ case AArch64::LDRXroX:
+ case AArch64::LDRXui:
+ case AArch64::LDURXi:
+ case AArch64::LDTRXi:
+ case AArch64::LDNPXi:
+ case AArch64::LDPXi:
+ case AArch64::LDPXpost:
+ case AArch64::LDPXpre:
+ isLoad = true;
+ break;
+ default:
+ break;
+ }
+
+ return isLoad;
+ }
+
+ bool isLDRS(const MCInst &Inst) const {
+ const unsigned opcode = Inst.getOpcode();
+ bool isLoad = false;
+ switch (opcode) {
+ case AArch64::LDRSui:
+ case AArch64::LDRSroW:
+ case AArch64::LDRSroX:
+ case AArch64::LDURSi:
+ case AArch64::LDPSi:
+ case AArch64::LDNPSi:
+ case AArch64::LDRSpre:
+ case AArch64::LDRSpost:
+ case AArch64::LDPSpost:
+ case AArch64::LDPSpre:
+ isLoad = true;
+ break;
+ default:
+ break;
+ }
+
+ return isLoad;
+ }
+
+ bool isLDRD(const MCInst &Inst) const {
+ const unsigned opcode = Inst.getOpcode();
+ bool isLoad = false;
+ switch (opcode) {
+ case AArch64::LDRDui:
+ case AArch64::LDRDpre:
+ case AArch64::LDRDpost:
+ case AArch64::LDRDroW:
+ case AArch64::LDRDroX:
+ case AArch64::LDURDi:
+ case AArch64::LDPDi:
+ case AArch64::LDNPDi:
+ case AArch64::LDPDpost:
+ case AArch64::LDPDpre:
+ isLoad = true;
+ break;
+ default:
+ break;
+ }
+
+ return isLoad;
+ }
+
+ bool isLDRQ(const MCInst &Inst) const {
+ const unsigned opcode = Inst.getOpcode();
+ bool isLoad = false;
+ switch (opcode) {
+ case AArch64::LDRQui:
+ case AArch64::LDRQpre:
+ case AArch64::LDRQpost:
+ case AArch64::LDRQroW:
+ case AArch64::LDRQroX:
+ case AArch64::LDURQi:
+ case AArch64::LDPQi:
+ case AArch64::LDNPQi:
+ case AArch64::LDPQpost:
+ case AArch64::LDPQpre:
+ isLoad = true;
+ break;
+ default:
+ break;
+ }
+ return isLoad;
}
bool mayLoad(const MCInst &Inst) const override {
- return isLDRB(Inst) || isLDRH(Inst) || isLDRW(Inst) || isLDRX(Inst);
+ return isLDRB(Inst) || isLDRH(Inst) || isLDRW(Inst) || isLDRX(Inst) ||
+ isLDRQ(Inst) || isLDRD(Inst) || isLDRS(Inst);
}
bool isAArch64ExclusiveLoad(const MCInst &Inst) const override {
@@ -1140,7 +1301,229 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
Inst.addOperand(MCOperand::createImm(0));
}
- bool mayStore(const MCInst &Inst) const override { return false; }
+ bool isStorePair(const MCInst &Inst) const {
+ const unsigned opcode = Inst.getOpcode();
+
+ auto isStorePairImmOffset = [&]() {
+ bool isStorePair = false;
+ switch (opcode) {
+ case AArch64::STPWi:
+ case AArch64::STPXi:
+ case AArch64::STPSi:
+ case AArch64::STPDi:
+ case AArch64::STPQi:
+ case AArch64::STNPWi:
+ case AArch64::STNPXi:
+ case AArch64::STNPSi:
+ case AArch64::STNPDi:
+ case AArch64::STNPQi:
+ isStorePair = true;
+ break;
+
+ default:
+ break;
+ }
+
+ return isStorePair;
+ };
+
+ auto isStorePairPostIndex = [&]() {
+ bool isStorePair = false;
+ switch (opcode) {
+ case AArch64::STPWpost:
+ case AArch64::STPXpost:
+ case AArch64::STPSpost:
+ case AArch64::STPDpost:
+ case AArch64::STPQpost:
+ isStorePair = true;
+ break;
+
+ default:
+ break;
+ }
+
+ return isStorePair;
+ };
+
+ auto isStorePairPreIndex = [&]() {
+ bool isStorePair = false;
+ switch (opcode) {
+ case AArch64::STPWpre:
+ case AArch64::STPXpre:
+ case AArch64::STPSpre:
+ case AArch64::STPDpre:
+ case AArch64::STPQpre:
+ isStorePair = true;
+ break;
+
+ default:
+ break;
+ }
+
+ return isStorePair;
+ };
+
+ return isStorePairImmOffset() || isStorePairPostIndex() ||
+ isStorePairPreIndex();
+ }
+
+ bool isStoreReg(const MCInst &Inst) const {
+ const unsigned opcode = Inst.getOpcode();
+ bool isStore = false;
+
+ auto isStoreRegUnscaleImm = [&]() {
+ switch (opcode) {
+ case AArch64::STURBi:
+ case AArch64::STURBBi:
+ case AArch64::STURHi:
+ case AArch64::STURHHi:
+ case AArch64::STURWi:
+ case AArch64::STURXi:
+ case AArch64::STURSi:
+ case AArch64::STURDi:
+ case AArch64::STURQi:
+ isStore = true;
+ break;
+
+ default:
+ break;
+ }
+
+ return isStore;
+ };
+
+ auto isStoreRegScaledImm = [&]() {
+ switch (opcode) {
+ case AArch64::STRBui:
+ case AArch64::STRBBui:
+ case AArch64::STRHui:
+ case AArch64::STRHHui:
+ case AArch64::STRWui:
+ case AArch64::STRXui:
+ case AArch64::STRSui:
+ case AArch64::STRDui:
+ case AArch64::STRQui:
+ isStore = true;
+ break;
+
+ default:
+ break;
+ }
+
+ return isStore;
+ };
+
+ auto isStoreRegImmPostIndexed = [&]() {
+ switch (opcode) {
+ case AArch64::STRBpost:
+ case AArch64::STRBBpost:
+ case AArch64::STRHpost:
+ case AArch64::STRHHpost:
+ case AArch64::STRWpost:
+ case AArch64::STRXpost:
+ case AArch64::STRSpost:
+ case AArch64::STRDpost:
+ case AArch64::STRQpost:
+ isStore = true;
+ break;
+
+ default:
+ break;
+ }
+
+ return isStore;
+ };
+
+ auto isStoreRegImmPreIndexed = [&]() {
+ switch (opcode) {
+ case AArch64::STRBpre:
+ case AArch64::STRBBpre:
+ case AArch64::STRHpre:
+ case AArch64::STRHHpre:
+ case AArch64::STRWpre:
+ case AArch64::STRXpre:
+ case AArch64::STRSpre:
+ case AArch64::STRDpre:
+ case AArch64::STRQpre:
+ isStore = true;
+ break;
+
+ default:
+ break;
+ }
+
+ return isStore;
+ };
+
+ auto isStoreRegUnscaleUnpriv = [&]() {
+ switch (opcode) {
+ case AArch64::STTRBi:
+ case AArch64::STTRHi:
+ case AArch64::STTRWi:
+ case AArch64::STTRXi:
+ isStore = true;
+ break;
+
+ default:
+ break;
+ }
+
+ return isStore;
+ };
+
+ auto isStoreRegTrunc = [&]() {
+ switch (opcode) {
+ case AArch64::STRBBroW:
+ case AArch64::STRBBroX:
+ case AArch64::STRBroW:
+ case AArch64::STRBroX:
+ case AArch64::STRDroW:
+ case AArch64::STRDroX:
+ case AArch64::STRHHroW:
+ case AArch64::STRHHroX:
+ case AArch64::STRHroW:
+ case AArch64::STRHroX:
+ case AArch64::STRQroW:
+ case AArch64::STRQroX:
+ case AArch64::STRSroW:
+ case AArch64::STRSroX:
+ case AArch64::STRWroW:
+ case AArch64::STRWroX:
+ case AArch64::STRXroW:
+ case AArch64::STRXroX:
+ isStore = true;
+ break;
+
+ default:
+ break;
+ }
+
+ return isStore;
+ };
+
+ return isStoreRegUnscaleImm() || isStoreRegScaledImm() ||
+ isStoreRegImmPreIndexed() || isStoreRegImmPostIndexed() ||
+ isStoreRegUnscaleUnpriv() || isStoreRegTrunc();
+ }
+
+ bool mayStore(const MCInst &Inst) const override {
+ return isStorePair(Inst) || isStoreReg(Inst) ||
+ isAArch64ExclusiveStore(Inst);
+ }
+
+ bool isStoreToStack(const MCInst &Inst) const {
+ if (!mayStore(Inst))
+ return false;
+ for (const MCOperand &Operand : useOperands(Inst)) {
+ if (!Operand.isReg())
+ continue;
+ unsigned Reg = Operand.getReg();
+ if (Reg == AArch64::SP || Reg == AArch64::WSP || Reg == AArch64::FP ||
+ Reg == AArch64::W29)
+ return true;
+ }
+ return false;
+ }
void createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
bool IsTailCall) override {
>From 50ce52080871ccff30ea6efd1a5fdfaf74a2137b Mon Sep 17 00:00:00 2001
From: Alexey Moksyakov <yavtuk at yandex.ru>
Date: Fri, 10 Jan 2025 15:22:15 +0300
Subject: [PATCH 2/2] Fixed comment, return true/false directly
---
.../Target/AArch64/AArch64MCPlusBuilder.cpp | 142 ++++++------------
1 file changed, 48 insertions(+), 94 deletions(-)
diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
index 994ec58ea83de0..170da35690b568 100644
--- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
+++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
@@ -225,7 +225,6 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
bool isLDRB(const MCInst &Inst) const {
const unsigned opcode = Inst.getOpcode();
- bool isLoad = false;
switch (opcode) {
case AArch64::LDRBpost:
case AArch64::LDRBBpost:
@@ -254,17 +253,15 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::LDTRBi:
case AArch64::LDTRSBWi:
case AArch64::LDTRSBXi:
- isLoad = true;
- break;
+ return true;
default:
- break;
+ return false;
}
- return isLoad;
+ llvm_unreachable("");
}
bool isLDRH(const MCInst &Inst) const {
const unsigned opcode = Inst.getOpcode();
- bool isLoad = false;
switch (opcode) {
case AArch64::LDRHpost:
case AArch64::LDRHHpost:
@@ -293,17 +290,15 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::LDTRHi:
case AArch64::LDTRSHWi:
case AArch64::LDTRSHXi:
- isLoad = true;
- break;
+ return true;
default:
- break;
+ return false;
}
- return isLoad;
+ llvm_unreachable("");
}
bool isLDRW(const MCInst &Inst) const {
const unsigned opcode = Inst.getOpcode();
- bool isLoad = false;
switch (opcode) {
case AArch64::LDRWpost:
case AArch64::LDRWpre:
@@ -326,16 +321,15 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::LDPSWpost:
case AArch64::LDPSWpre:
case AArch64::LDNPWi:
- isLoad = true;
+ return true;
default:
- break;
+ return false;
}
- return isLoad;
+ llvm_unreachable("");
}
bool isLDRX(const MCInst &Inst) const {
const unsigned opcode = Inst.getOpcode();
- bool isLoad = false;
switch (opcode) {
case AArch64::LDRXpost:
case AArch64::LDRXpre:
@@ -348,18 +342,15 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::LDPXi:
case AArch64::LDPXpost:
case AArch64::LDPXpre:
- isLoad = true;
- break;
+ return true;
default:
- break;
+ return false;
}
-
- return isLoad;
+ llvm_unreachable("");
}
bool isLDRS(const MCInst &Inst) const {
const unsigned opcode = Inst.getOpcode();
- bool isLoad = false;
switch (opcode) {
case AArch64::LDRSui:
case AArch64::LDRSroW:
@@ -371,18 +362,15 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::LDRSpost:
case AArch64::LDPSpost:
case AArch64::LDPSpre:
- isLoad = true;
- break;
+ return true;
default:
- break;
+ return false;
}
-
- return isLoad;
+ llvm_unreachable("");
}
bool isLDRD(const MCInst &Inst) const {
const unsigned opcode = Inst.getOpcode();
- bool isLoad = false;
switch (opcode) {
case AArch64::LDRDui:
case AArch64::LDRDpre:
@@ -394,18 +382,15 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::LDNPDi:
case AArch64::LDPDpost:
case AArch64::LDPDpre:
- isLoad = true;
- break;
+ return true;
default:
- break;
+ return false;
}
-
- return isLoad;
+ llvm_unreachable("");
}
bool isLDRQ(const MCInst &Inst) const {
const unsigned opcode = Inst.getOpcode();
- bool isLoad = false;
switch (opcode) {
case AArch64::LDRQui:
case AArch64::LDRQpre:
@@ -417,12 +402,11 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::LDNPQi:
case AArch64::LDPQpost:
case AArch64::LDPQpre:
- isLoad = true;
- break;
+ return true;
default:
- break;
+ return false;
}
- return isLoad;
+ llvm_unreachable("");
}
bool mayLoad(const MCInst &Inst) const override {
@@ -1305,7 +1289,6 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
const unsigned opcode = Inst.getOpcode();
auto isStorePairImmOffset = [&]() {
- bool isStorePair = false;
switch (opcode) {
case AArch64::STPWi:
case AArch64::STPXi:
@@ -1317,50 +1300,40 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::STNPSi:
case AArch64::STNPDi:
case AArch64::STNPQi:
- isStorePair = true;
- break;
-
+ return true;
default:
- break;
+ return false;
}
- return isStorePair;
+ llvm_unreachable("");
};
auto isStorePairPostIndex = [&]() {
- bool isStorePair = false;
switch (opcode) {
case AArch64::STPWpost:
case AArch64::STPXpost:
case AArch64::STPSpost:
case AArch64::STPDpost:
case AArch64::STPQpost:
- isStorePair = true;
- break;
-
+ return true;
default:
- break;
+ return false;
}
-
- return isStorePair;
+ llvm_unreachable("");
};
auto isStorePairPreIndex = [&]() {
- bool isStorePair = false;
switch (opcode) {
case AArch64::STPWpre:
case AArch64::STPXpre:
case AArch64::STPSpre:
case AArch64::STPDpre:
case AArch64::STPQpre:
- isStorePair = true;
- break;
-
+ return true;
default:
- break;
+ return false;
}
-
- return isStorePair;
+ llvm_unreachable("");
};
return isStorePairImmOffset() || isStorePairPostIndex() ||
@@ -1369,7 +1342,6 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
bool isStoreReg(const MCInst &Inst) const {
const unsigned opcode = Inst.getOpcode();
- bool isStore = false;
auto isStoreRegUnscaleImm = [&]() {
switch (opcode) {
@@ -1382,14 +1354,11 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::STURSi:
case AArch64::STURDi:
case AArch64::STURQi:
- isStore = true;
- break;
-
+ return true;
default:
- break;
+ return false;
}
-
- return isStore;
+ llvm_unreachable("");
};
auto isStoreRegScaledImm = [&]() {
@@ -1403,14 +1372,11 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::STRSui:
case AArch64::STRDui:
case AArch64::STRQui:
- isStore = true;
- break;
-
+ return true;
default:
- break;
+ return false;
}
-
- return isStore;
+ llvm_unreachable("");
};
auto isStoreRegImmPostIndexed = [&]() {
@@ -1424,14 +1390,11 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::STRSpost:
case AArch64::STRDpost:
case AArch64::STRQpost:
- isStore = true;
- break;
-
+ return true;
default:
- break;
+ return false;
}
-
- return isStore;
+ llvm_unreachable("");
};
auto isStoreRegImmPreIndexed = [&]() {
@@ -1445,14 +1408,11 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::STRSpre:
case AArch64::STRDpre:
case AArch64::STRQpre:
- isStore = true;
- break;
-
+ return true;
default:
- break;
+ return false;
}
-
- return isStore;
+ llvm_unreachable("");
};
auto isStoreRegUnscaleUnpriv = [&]() {
@@ -1461,14 +1421,11 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::STTRHi:
case AArch64::STTRWi:
case AArch64::STTRXi:
- isStore = true;
- break;
-
+ return true;
default:
- break;
+ return false;
}
-
- return isStore;
+ llvm_unreachable("");
};
auto isStoreRegTrunc = [&]() {
@@ -1491,14 +1448,11 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
case AArch64::STRWroX:
case AArch64::STRXroW:
case AArch64::STRXroX:
- isStore = true;
- break;
-
+ return true;
default:
- break;
+ return false;
}
-
- return isStore;
+ llvm_unreachable("");
};
return isStoreRegUnscaleImm() || isStoreRegScaledImm() ||
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