[llvm] [CodeGen] Add MachineRegisterClassInfo analysis pass (PR #120690)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 10 03:30:32 PST 2025
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/120690
>From 95ed02cb9b344cce1ed0b89b0a3e87790bcbb154 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Fri, 20 Dec 2024 15:18:15 +0800
Subject: [PATCH] [CodeGen] Add MachineRegisterClassInfo analysis pass
Which is a wrapper of `RegisterClassInfo`.
This can cache the result of `RegisterClassInfo` and hence
we can reduce compile time.
---
llvm/include/llvm/CodeGen/MachinePipeliner.h | 2 +-
.../llvm/CodeGen/MachineRegisterClassInfo.h | 57 +++++++++++++++++++
llvm/include/llvm/CodeGen/MachineScheduler.h | 6 --
llvm/include/llvm/InitializePasses.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +
llvm/lib/CodeGen/BreakFalseDeps.cpp | 10 ++--
llvm/lib/CodeGen/CMakeLists.txt | 1 +
llvm/lib/CodeGen/MachineCombiner.cpp | 9 ++-
llvm/lib/CodeGen/MachineLICM.cpp | 1 +
llvm/lib/CodeGen/MachinePipeliner.cpp | 10 +++-
llvm/lib/CodeGen/MachineRegisterClassInfo.cpp | 50 ++++++++++++++++
llvm/lib/CodeGen/MachineScheduler.cpp | 13 ++---
llvm/lib/CodeGen/MachineSink.cpp | 11 ++--
llvm/lib/CodeGen/PostRASchedulerList.cpp | 15 +++--
llvm/lib/CodeGen/RegisterCoalescer.cpp | 11 ++--
llvm/lib/CodeGen/ShrinkWrap.cpp | 9 ++-
llvm/lib/Passes/PassBuilder.cpp | 1 +
.../AArch64/AArch64A57FPLoadBalancing.cpp | 10 +++-
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 19 ++++---
llvm/test/CodeGen/AArch64/O3-pipeline.ll | 1 +
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll | 8 +++
.../CodeGen/AMDGPU/sgpr-regalloc-flags.ll | 1 +
llvm/test/CodeGen/ARM/O3-pipeline.ll | 1 +
llvm/test/CodeGen/LoongArch/opt-pipeline.ll | 1 +
llvm/test/CodeGen/PowerPC/O3-pipeline.ll | 1 +
llvm/test/CodeGen/RISCV/O3-pipeline.ll | 1 +
llvm/test/CodeGen/X86/opt-pipeline.ll | 2 +
27 files changed, 201 insertions(+), 53 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h
create mode 100644 llvm/lib/CodeGen/MachineRegisterClassInfo.cpp
diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h
index 8e47d0cead7571..5ae44b50b99f3d 100644
--- a/llvm/include/llvm/CodeGen/MachinePipeliner.h
+++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h
@@ -74,7 +74,7 @@ class MachinePipeliner : public MachineFunctionPass {
const MachineDominatorTree *MDT = nullptr;
const InstrItineraryData *InstrItins = nullptr;
const TargetInstrInfo *TII = nullptr;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo = nullptr;
bool disabledByPragma = false;
unsigned II_setByPragma = 0;
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h
new file mode 100644
index 00000000000000..dd8e34cab0bddf
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h
@@ -0,0 +1,57 @@
+//=- MachineRegisterClassInfo.h - Machine Register Class Info -----*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This analysis calculates register class info via RegisterClassInfo.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINEREGISTERCLASSINFO_H
+#define LLVM_CODEGEN_MACHINEREGISTERCLASSINFO_H
+
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/Pass.h"
+
+namespace llvm {
+
+class MachineRegisterClassInfoAnalysis
+ : public AnalysisInfoMixin<MachineRegisterClassInfoAnalysis> {
+ friend AnalysisInfoMixin<MachineRegisterClassInfoAnalysis>;
+
+ static AnalysisKey Key;
+
+public:
+ using Result = RegisterClassInfo;
+
+ Result run(MachineFunction &, MachineFunctionAnalysisManager &);
+};
+
+class MachineRegisterClassInfoWrapperPass : public MachineFunctionPass {
+ virtual void anchor();
+
+ RegisterClassInfo RCI;
+
+public:
+ static char ID;
+
+ MachineRegisterClassInfoWrapperPass();
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesAll();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ RegisterClassInfo &getRCI() { return RCI; }
+ const RegisterClassInfo &getRCI() const { return RCI; }
+};
+} // namespace llvm
+
+#endif
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 3dd62b2ba333c3..44698e04e1e8bf 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -140,13 +140,7 @@ struct MachineSchedContext {
const TargetPassConfig *PassConfig = nullptr;
AAResults *AA = nullptr;
LiveIntervals *LIS = nullptr;
-
RegisterClassInfo *RegClassInfo;
-
- MachineSchedContext();
- MachineSchedContext &operator=(const MachineSchedContext &other) = delete;
- MachineSchedContext(const MachineSchedContext &other) = delete;
- virtual ~MachineSchedContext();
};
/// MachineSchedRegistry provides a selection of available machine instruction
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 1cb9013bc48cc5..e4f6aced3ae454 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -208,6 +208,7 @@ void initializeMachineOutlinerPass(PassRegistry &);
void initializeMachinePipelinerPass(PassRegistry &);
void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializeMachineRegionInfoPassPass(PassRegistry &);
+void initializeMachineRegisterClassInfoWrapperPassPass(PassRegistry &);
void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &);
void initializeMachineSchedulerPass(PassRegistry &);
void initializeMachineSinkingPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 29763995e8b516..8471960356b090 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -112,6 +112,8 @@ MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter",
MachineOptimizationRemarkEmitterAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree",
MachinePostDominatorTreeAnalysis())
+MACHINE_FUNCTION_ANALYSIS("machine-reg-class-info",
+ MachineRegisterClassInfoAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", MachineTraceMetricsAnalysis())
MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC))
MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis())
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index 618e41894b29bc..fece3bf14a75d8 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -20,6 +20,7 @@
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/ReachingDefAnalysis.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
@@ -38,7 +39,7 @@ class BreakFalseDeps : public MachineFunctionPass {
MachineFunction *MF = nullptr;
const TargetInstrInfo *TII = nullptr;
const TargetRegisterInfo *TRI = nullptr;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo = nullptr;
/// List of undefined register reads in this block in forward order.
std::vector<std::pair<MachineInstr *, unsigned>> UndefReads;
@@ -58,6 +59,7 @@ class BreakFalseDeps : public MachineFunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
AU.addRequired<ReachingDefAnalysis>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -103,6 +105,7 @@ class BreakFalseDeps : public MachineFunctionPass {
char BreakFalseDeps::ID = 0;
INITIALIZE_PASS_BEGIN(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false)
INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false)
FunctionPass *llvm::createBreakFalseDeps() { return new BreakFalseDeps(); }
@@ -153,7 +156,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
// max clearance or clearance higher than Pref.
unsigned MaxClearance = 0;
unsigned MaxClearanceReg = OriginalReg;
- ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
+ ArrayRef<MCPhysReg> Order = RegClassInfo->getOrder(OpRC);
for (MCPhysReg Reg : Order) {
unsigned Clearance = RDA->getClearance(MI, Reg);
if (Clearance <= MaxClearance)
@@ -285,8 +288,7 @@ bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) {
TII = MF->getSubtarget().getInstrInfo();
TRI = MF->getSubtarget().getRegisterInfo();
RDA = &getAnalysis<ReachingDefAnalysis>();
-
- RegClassInfo.runOnMachineFunction(mf);
+ RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
LLVM_DEBUG(dbgs() << "********** BREAK FALSE DEPENDENCIES **********\n");
diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt
index 145fd2fac8b564..b5c0194d7ecd37 100644
--- a/llvm/lib/CodeGen/CMakeLists.txt
+++ b/llvm/lib/CodeGen/CMakeLists.txt
@@ -141,6 +141,7 @@ add_llvm_component_library(LLVMCodeGen
MachinePipeliner.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp
+ MachineRegisterClassInfo.cpp
MachineRegisterInfo.cpp
MachineScheduler.cpp
MachineSink.cpp
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index b8d59214a6ec32..0f3778a3cfb803 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineSizeOpts.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
@@ -73,7 +74,7 @@ class MachineCombiner : public MachineFunctionPass {
MachineTraceMetrics::Ensemble *TraceEnsemble = nullptr;
MachineBlockFrequencyInfo *MBFI = nullptr;
ProfileSummaryInfo *PSI = nullptr;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo = nullptr;
TargetSchedModel TSchedModel;
@@ -131,6 +132,7 @@ INITIALIZE_PASS_BEGIN(MachineCombiner, DEBUG_TYPE,
"Machine InstCombiner", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineTraceMetricsWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(MachineCombiner, DEBUG_TYPE, "Machine InstCombiner",
false, false)
@@ -143,6 +145,7 @@ void MachineCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<MachineTraceMetricsWrapperPass>();
AU.addRequired<LazyMachineBlockFrequencyInfoPass>();
AU.addRequired<ProfileSummaryInfoWrapperPass>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -571,7 +574,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
bool OptForSize = llvm::shouldOptimizeForSize(MBB, PSI, MBFI);
bool DoRegPressureReduce =
- TII->shouldReduceRegisterPressure(MBB, &RegClassInfo);
+ TII->shouldReduceRegisterPressure(MBB, RegClassInfo);
while (BlockIter != MBB->end()) {
auto &MI = *BlockIter++;
@@ -730,7 +733,7 @@ bool MachineCombiner::runOnMachineFunction(MachineFunction &MF) {
&getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI() :
nullptr;
TraceEnsemble = nullptr;
- RegClassInfo.runOnMachineFunction(MF);
+ RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
LLVM_DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n');
if (!TII->useMachineCombiner()) {
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index d1d5509dc482a2..976bd893561726 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -33,6 +33,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index acd42aa497c6fe..2c42f4de6556d2 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -58,6 +58,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ModuloSchedule.h"
#include "llvm/CodeGen/Register.h"
@@ -234,6 +235,7 @@ INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(MachinePipeliner, DEBUG_TYPE,
"Modulo Software Pipelining", false, false)
@@ -263,8 +265,8 @@ bool MachinePipeliner::runOnMachineFunction(MachineFunction &mf) {
MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
+ RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
TII = MF->getSubtarget().getInstrInfo();
- RegClassInfo.runOnMachineFunction(*MF);
for (const auto &L : *MLI)
scheduleLoop(*L);
@@ -471,7 +473,7 @@ bool MachinePipeliner::swingModuloScheduler(MachineLoop &L) {
assert(L.getBlocks().size() == 1 && "SMS works on single blocks only.");
SwingSchedulerDAG SMS(
- *this, L, getAnalysis<LiveIntervalsWrapperPass>().getLIS(), RegClassInfo,
+ *this, L, getAnalysis<LiveIntervalsWrapperPass>().getLIS(), *RegClassInfo,
II_setByPragma, LI.LoopPipelinerInfo.get());
MachineBasicBlock *MBB = L.getHeader();
@@ -503,6 +505,7 @@ void MachinePipeliner::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addRequired<MachineOptimizationRemarkEmitterPass>();
AU.addRequired<TargetPassConfig>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -514,7 +517,8 @@ bool MachinePipeliner::runWindowScheduler(MachineLoop &L) {
Context.PassConfig = &getAnalysis<TargetPassConfig>();
Context.AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
Context.LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
- Context.RegClassInfo->runOnMachineFunction(*MF);
+ Context.RegClassInfo =
+ &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
WindowScheduler WS(&Context, L);
return WS.run();
}
diff --git a/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp b/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp
new file mode 100644
index 00000000000000..9d8138ec391a58
--- /dev/null
+++ b/llvm/lib/CodeGen/MachineRegisterClassInfo.cpp
@@ -0,0 +1,50 @@
+//===- MachineRegisterClassInfo.cpp - Machine Register Class Info ---------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This analysis calculates register class info via RegisterClassInfo.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
+#include "llvm/InitializePasses.h"
+
+using namespace llvm;
+
+INITIALIZE_PASS_BEGIN(MachineRegisterClassInfoWrapperPass,
+ "machine-reg-class-info",
+ "Machine Register Class Info Analysis", false, true)
+INITIALIZE_PASS_END(MachineRegisterClassInfoWrapperPass,
+ "machine-reg-class-info",
+ "Machine Register Class Info Analysis", false, true)
+
+MachineRegisterClassInfoAnalysis::Result
+MachineRegisterClassInfoAnalysis::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &) {
+ RegisterClassInfo RCI;
+ RCI.runOnMachineFunction(MF);
+ return RCI;
+}
+
+char MachineRegisterClassInfoWrapperPass::ID = 0;
+
+MachineRegisterClassInfoWrapperPass::MachineRegisterClassInfoWrapperPass()
+ : MachineFunctionPass(ID), RCI() {
+ PassRegistry &Registry = *PassRegistry::getPassRegistry();
+ initializeMachineRegisterClassInfoWrapperPassPass(Registry);
+}
+
+bool MachineRegisterClassInfoWrapperPass::runOnMachineFunction(
+ MachineFunction &MF) {
+ RCI.runOnMachineFunction(MF);
+ return false;
+}
+
+void MachineRegisterClassInfoWrapperPass::anchor() {}
+
+AnalysisKey MachineRegisterClassInfoAnalysis::Key;
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 91aaeea156c4a1..4b283f31ec3e5a 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -31,6 +31,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
@@ -205,14 +206,6 @@ void ScheduleDAGMutation::anchor() {}
// Machine Instruction Scheduling Pass and Registry
//===----------------------------------------------------------------------===//
-MachineSchedContext::MachineSchedContext() {
- RegClassInfo = new RegisterClassInfo();
-}
-
-MachineSchedContext::~MachineSchedContext() {
- delete RegClassInfo;
-}
-
namespace {
/// Base class for a machine scheduler class that can run at any point.
@@ -287,6 +280,7 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addPreserved<LiveIntervalsWrapperPass>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -299,6 +293,7 @@ INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched",
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(PostMachineScheduler, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
@@ -455,7 +450,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
LLVM_DEBUG(LIS->dump());
MF->verify(this, "Before machine scheduling.", &errs());
}
- RegClassInfo->runOnMachineFunction(*MF);
+ RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
// Instantiate the selected scheduler for this target, function, and
// optimization level.
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 3c816f97650901..8470d92505a114 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -38,6 +38,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePostDominators.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineSizeOpts.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -127,7 +128,7 @@ class MachineSinking : public MachineFunctionPass {
MachineBlockFrequencyInfo *MBFI = nullptr;
const MachineBranchProbabilityInfo *MBPI = nullptr;
AliasAnalysis *AA = nullptr;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo = nullptr;
// Remember which edges have been considered for breaking.
SmallSet<std::pair<MachineBasicBlock *, MachineBasicBlock *>, 8>
@@ -200,6 +201,7 @@ class MachineSinking : public MachineFunctionPass {
AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
AU.addPreserved<MachineCycleInfoWrapperPass>();
AU.addPreserved<MachineLoopInfoWrapperPass>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
AU.addRequired<ProfileSummaryInfoWrapperPass>();
if (UseBlockFreqInfo)
AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
@@ -290,6 +292,7 @@ INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_END(MachineSinking, DEBUG_TYPE, "Machine code sinking", false,
false)
@@ -731,7 +734,7 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
: nullptr;
MBPI = &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
- RegClassInfo.runOnMachineFunction(MF);
+ RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
@@ -1068,7 +1071,7 @@ MachineSinking::getBBRegisterPressure(const MachineBasicBlock &MBB) {
RegPressureTracker RPTracker(Pressure);
// Initialize the register pressure tracker.
- RPTracker.init(MBB.getParent(), &RegClassInfo, nullptr, &MBB, MBB.end(),
+ RPTracker.init(MBB.getParent(), RegClassInfo, nullptr, &MBB, MBB.end(),
/*TrackLaneMasks*/ false, /*TrackUntiedDefs=*/true);
for (MachineBasicBlock::const_iterator MII = MBB.instr_end(),
@@ -1098,7 +1101,7 @@ bool MachineSinking::registerPressureSetExceedsLimit(
std::vector<unsigned> BBRegisterPressure = getBBRegisterPressure(MBB);
for (; *PS != -1; PS++)
if (Weight + BBRegisterPressure[*PS] >=
- RegClassInfo.getRegPressureSetLimit(*PS))
+ RegClassInfo->getRegPressureSetLimit(*PS))
return true;
return false;
}
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp
index badfd9a68d6a01..bcef64be4b2c16 100644
--- a/llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -24,6 +24,7 @@
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
@@ -75,7 +76,7 @@ AntiDepBreaker::~AntiDepBreaker() = default;
namespace {
class PostRAScheduler : public MachineFunctionPass {
const TargetInstrInfo *TII = nullptr;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo = nullptr;
public:
static char ID;
@@ -89,6 +90,7 @@ namespace {
AU.addPreserved<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
AU.addPreserved<MachineLoopInfoWrapperPass>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -190,8 +192,11 @@ namespace {
char &llvm::PostRASchedulerID = PostRAScheduler::ID;
-INITIALIZE_PASS(PostRAScheduler, DEBUG_TYPE,
- "Post RA top-down list latency scheduler", false, false)
+INITIALIZE_PASS_BEGIN(PostRAScheduler, DEBUG_TYPE,
+ "Post RA top-down list latency scheduler", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
+INITIALIZE_PASS_END(PostRAScheduler, DEBUG_TYPE,
+ "Post RA top-down list latency scheduler", false, false)
SchedulePostRATDList::SchedulePostRATDList(
MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA,
@@ -287,11 +292,11 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
}
SmallVector<const TargetRegisterClass *, 4> CriticalPathRCs;
Subtarget.getCriticalPathRCs(CriticalPathRCs);
- RegClassInfo.runOnMachineFunction(Fn);
+ RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
LLVM_DEBUG(dbgs() << "PostRAScheduler\n");
- SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
+ SchedulePostRATDList Scheduler(Fn, MLI, AA, *RegClassInfo, AntiDepMode,
CriticalPathRCs);
// Loop over all of the basic blocks
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 8313927dd2aa11..7f174d9a104840 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -31,6 +31,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -131,7 +132,7 @@ namespace {
LiveIntervals *LIS = nullptr;
const MachineLoopInfo* Loops = nullptr;
AliasAnalysis *AA = nullptr;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo = nullptr;
/// Position and VReg of a PHI instruction during coalescing.
struct PHIValPos {
@@ -410,6 +411,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(RegisterCoalescer, "register-coalescer",
"Register Coalescer", false, false)
@@ -594,6 +596,7 @@ void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<MachineLoopInfoWrapperPass>();
AU.addPreserved<MachineLoopInfoWrapperPass>();
AU.addPreservedID(MachineDominatorsID);
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -2199,7 +2202,7 @@ bool RegisterCoalescer::joinCopy(
// Removing sub-register copies can ease the register class constraints.
// Make sure we attempt to inflate the register class of DstReg.
- if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
+ if (!CP.isPhys() && RegClassInfo->isProperSubClass(CP.getNewRC()))
InflateRegs.push_back(CP.getDstReg());
// CopyMI has been erased by joinIntervals at this point. Remove it from
@@ -4261,6 +4264,8 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
+
if (EnableGlobalCopies == cl::BOU_UNSET)
JoinGlobalCopies = STI.enableJoinGlobalCopies();
else
@@ -4290,8 +4295,6 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
DbgVRegToValues.clear();
buildVRegToDbgValueMap(fn);
- RegClassInfo.runOnMachineFunction(fn);
-
// Join (coalesce) intervals if requested.
if (EnableJoining)
joinAllIntervals();
diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index 5029f45def2266..c863c17a7ba938 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -65,6 +65,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachinePostDominators.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
@@ -112,7 +113,7 @@ namespace {
/// are safe for such insertion.
class ShrinkWrap : public MachineFunctionPass {
/// Hold callee-saved information.
- RegisterClassInfo RCI;
+ RegisterClassInfo *RCI = nullptr;
MachineDominatorTree *MDT = nullptr;
MachinePostDominatorTree *MPDT = nullptr;
@@ -223,7 +224,7 @@ class ShrinkWrap : public MachineFunctionPass {
/// Initialize the pass for \p MF.
void init(MachineFunction &MF) {
- RCI.runOnMachineFunction(MF);
+ RCI = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
MPDT = &getAnalysis<MachinePostDominatorTreeWrapperPass>().getPostDomTree();
Save = nullptr;
@@ -265,6 +266,7 @@ class ShrinkWrap : public MachineFunctionPass {
AU.addRequired<MachinePostDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
AU.addRequired<MachineOptimizationRemarkEmitterPass>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -292,6 +294,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(ShrinkWrap, DEBUG_TYPE, "Shrink Wrap Pass", false, false)
bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS,
@@ -350,7 +353,7 @@ bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS,
// instruction we can ignore, otherwise we may pessimize shrinkwrapping.
UseOrDefCSR =
(!MI.isCall() && PhysReg == SP) ||
- RCI.getLastCalleeSavedAlias(PhysReg) ||
+ RCI->getLastCalleeSavedAlias(PhysReg) ||
(!MI.isReturn() && TRI->isNonallocatableRegisterCalleeSave(PhysReg));
} else if (MO.isRegMask()) {
// Check if this regmask clobbers any of the CSRs.
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index aac44077400550..aa903e891de3af 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -116,6 +116,7 @@
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachinePostDominators.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/MachineVerifier.h"
diff --git a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
index c27ec8e6dc6b34..7c780972f8875c 100644
--- a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
+++ b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
@@ -35,9 +35,11 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/InitializePasses.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
@@ -108,7 +110,7 @@ class Chain;
class AArch64A57FPLoadBalancing : public MachineFunctionPass {
MachineRegisterInfo *MRI;
const TargetRegisterInfo *TRI;
- RegisterClassInfo RCI;
+ RegisterClassInfo *RCI = nullptr;
public:
static char ID;
@@ -129,6 +131,7 @@ class AArch64A57FPLoadBalancing : public MachineFunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -152,6 +155,7 @@ char AArch64A57FPLoadBalancing::ID = 0;
INITIALIZE_PASS_BEGIN(AArch64A57FPLoadBalancing, DEBUG_TYPE,
"AArch64 A57 FP Load-Balancing", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(AArch64A57FPLoadBalancing, DEBUG_TYPE,
"AArch64 A57 FP Load-Balancing", false, false)
@@ -317,7 +321,7 @@ bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) {
MRI = &F.getRegInfo();
TRI = F.getRegInfo().getTargetRegisterInfo();
- RCI.runOnMachineFunction(F);
+ RCI = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
for (auto &MBB : F) {
Changed |= runOnBasicBlock(MBB);
@@ -515,7 +519,7 @@ int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C,
// Make sure we allocate in-order, to get the cheapest registers first.
unsigned RegClassID = ChainBegin->getDesc().operands()[0].RegClass;
- auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
+ auto Ord = RCI->getOrder(TRI->getRegClass(RegClassID));
for (auto Reg : Ord) {
if (!Units.available(Reg))
continue;
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index 205a45a045a420..7eb28cae69226b 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterClassInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
@@ -42,7 +43,7 @@ class SIPreAllocateWWMRegs {
LiveIntervals *LIS;
LiveRegMatrix *Matrix;
VirtRegMap *VRM;
- RegisterClassInfo RegClassInfo;
+ RegisterClassInfo *RegClassInfo;
std::vector<unsigned> RegsToRewrite;
#ifndef NDEBUG
@@ -53,8 +54,8 @@ class SIPreAllocateWWMRegs {
public:
SIPreAllocateWWMRegs(LiveIntervals *LIS, LiveRegMatrix *Matrix,
- VirtRegMap *VRM)
- : LIS(LIS), Matrix(Matrix), VRM(VRM) {}
+ VirtRegMap *VRM, RegisterClassInfo *RCI)
+ : LIS(LIS), Matrix(Matrix), VRM(VRM), RegClassInfo(RCI) {}
bool run(MachineFunction &MF);
};
@@ -70,6 +71,7 @@ class SIPreAllocateWWMRegsLegacy : public MachineFunctionPass {
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addRequired<VirtRegMapWrapperLegacy>();
AU.addRequired<LiveRegMatrixWrapperLegacy>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -82,6 +84,7 @@ INITIALIZE_PASS_BEGIN(SIPreAllocateWWMRegsLegacy, DEBUG_TYPE,
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrixWrapperLegacy)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(SIPreAllocateWWMRegsLegacy, DEBUG_TYPE,
"SI Pre-allocate WWM Registers", false, false)
@@ -106,7 +109,7 @@ bool SIPreAllocateWWMRegs::processDef(MachineOperand &MO) {
LiveInterval &LI = LIS->getInterval(Reg);
- for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
+ for (MCRegister PhysReg : RegClassInfo->getOrder(MRI->getRegClass(Reg))) {
if (!MRI->isPhysRegUsed(PhysReg, /*SkipRegMaskTest=*/true) &&
Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) {
Matrix->assign(LI, PhysReg);
@@ -192,7 +195,8 @@ bool SIPreAllocateWWMRegsLegacy::runOnMachineFunction(MachineFunction &MF) {
auto *LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
auto *Matrix = &getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
auto *VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
- return SIPreAllocateWWMRegs(LIS, Matrix, VRM).run(MF);
+ auto *RCI = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
+ return SIPreAllocateWWMRegs(LIS, Matrix, VRM, RCI).run(MF);
}
bool SIPreAllocateWWMRegs::run(MachineFunction &MF) {
@@ -204,8 +208,6 @@ bool SIPreAllocateWWMRegs::run(MachineFunction &MF) {
TRI = &TII->getRegisterInfo();
MRI = &MF.getRegInfo();
- RegClassInfo.runOnMachineFunction(MF);
-
bool PreallocateSGPRSpillVGPRs =
EnablePreallocateSGPRSpillVGPRs ||
MF.getFunction().hasFnAttribute("amdgpu-prealloc-sgpr-spill-vgprs");
@@ -265,6 +267,7 @@ SIPreAllocateWWMRegsPass::run(MachineFunction &MF,
auto *LIS = &MFAM.getResult<LiveIntervalsAnalysis>(MF);
auto *Matrix = &MFAM.getResult<LiveRegMatrixAnalysis>(MF);
auto *VRM = &MFAM.getResult<VirtRegMapAnalysis>(MF);
- SIPreAllocateWWMRegs(LIS, Matrix, VRM).run(MF);
+ auto *RCI = &MFAM.getResult<MachineRegisterClassInfoAnalysis>(MF);
+ SIPreAllocateWWMRegs(LIS, Matrix, VRM, RCI).run(MF);
return PreservedAnalyses::all();
}
diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
index b5d5e27afa17ad..dab6218015b4ac 100644
--- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -138,6 +138,7 @@
; CHECK-NEXT: Machine Trace Metrics
; CHECK-NEXT: AArch64 Conditional Compares
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Machine InstCombiner
; CHECK-NEXT: AArch64 Conditional Branch Tuning
; CHECK-NEXT: Machine Trace Metrics
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index e77f4f69e265bb..b1ea647602ad4b 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -120,6 +120,7 @@
; GCN-O0-NEXT: Live Interval Analysis
; GCN-O0-NEXT: Virtual Register Map
; GCN-O0-NEXT: Live Register Matrix
+; GCN-O0-NEXT: Machine Register Class Info Analysis
; GCN-O0-NEXT: SI Pre-allocate WWM Registers
; GCN-O0-NEXT: Fast Register Allocator
; GCN-O0-NEXT: SI Lower WWM Copies
@@ -368,6 +369,7 @@
; GCN-O1-NEXT: SI lower SGPR spill instructions
; GCN-O1-NEXT: Virtual Register Map
; GCN-O1-NEXT: Live Register Matrix
+; GCN-O1-NEXT: Machine Register Class Info Analysis
; GCN-O1-NEXT: SI Pre-allocate WWM Registers
; GCN-O1-NEXT: Live Stack Slot Analysis
; GCN-O1-NEXT: Greedy Register Allocator
@@ -622,6 +624,7 @@
; GCN-O1-OPTS-NEXT: Machine Common Subexpression Elimination
; GCN-O1-OPTS-NEXT: MachinePostDominator Tree Construction
; GCN-O1-OPTS-NEXT: Machine Cycle Info Analysis
+; GCN-O1-OPTS-NEXT: Machine Register Class Info Analysis
; GCN-O1-OPTS-NEXT: Machine code sinking
; GCN-O1-OPTS-NEXT: Peephole Optimizations
; GCN-O1-OPTS-NEXT: Remove dead machine instructions
@@ -676,6 +679,7 @@
; GCN-O1-OPTS-NEXT: SI lower SGPR spill instructions
; GCN-O1-OPTS-NEXT: Virtual Register Map
; GCN-O1-OPTS-NEXT: Live Register Matrix
+; GCN-O1-OPTS-NEXT: Machine Register Class Info Analysis
; GCN-O1-OPTS-NEXT: SI Pre-allocate WWM Registers
; GCN-O1-OPTS-NEXT: Live Stack Slot Analysis
; GCN-O1-OPTS-NEXT: Greedy Register Allocator
@@ -935,6 +939,7 @@
; GCN-O2-NEXT: Machine Common Subexpression Elimination
; GCN-O2-NEXT: MachinePostDominator Tree Construction
; GCN-O2-NEXT: Machine Cycle Info Analysis
+; GCN-O2-NEXT: Machine Register Class Info Analysis
; GCN-O2-NEXT: Machine code sinking
; GCN-O2-NEXT: Peephole Optimizations
; GCN-O2-NEXT: Remove dead machine instructions
@@ -990,6 +995,7 @@
; GCN-O2-NEXT: SI lower SGPR spill instructions
; GCN-O2-NEXT: Virtual Register Map
; GCN-O2-NEXT: Live Register Matrix
+; GCN-O2-NEXT: Machine Register Class Info Analysis
; GCN-O2-NEXT: SI Pre-allocate WWM Registers
; GCN-O2-NEXT: Live Stack Slot Analysis
; GCN-O2-NEXT: Greedy Register Allocator
@@ -1262,6 +1268,7 @@
; GCN-O3-NEXT: Machine Common Subexpression Elimination
; GCN-O3-NEXT: MachinePostDominator Tree Construction
; GCN-O3-NEXT: Machine Cycle Info Analysis
+; GCN-O3-NEXT: Machine Register Class Info Analysis
; GCN-O3-NEXT: Machine code sinking
; GCN-O3-NEXT: Peephole Optimizations
; GCN-O3-NEXT: Remove dead machine instructions
@@ -1317,6 +1324,7 @@
; GCN-O3-NEXT: SI lower SGPR spill instructions
; GCN-O3-NEXT: Virtual Register Map
; GCN-O3-NEXT: Live Register Matrix
+; GCN-O3-NEXT: Machine Register Class Info Analysis
; GCN-O3-NEXT: SI Pre-allocate WWM Registers
; GCN-O3-NEXT: Live Stack Slot Analysis
; GCN-O3-NEXT: Greedy Register Allocator
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll b/llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
index 52ad7e5355207d..c14728e283749a 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
@@ -21,6 +21,7 @@
; DEFAULT-NEXT: SI lower SGPR spill instructions
; DEFAULT-NEXT: Virtual Register Map
; DEFAULT-NEXT: Live Register Matrix
+; DEFAULT-NEXT: Machine Register Class Info Analysis
; DEFAULT-NEXT: SI Pre-allocate WWM Registers
; DEFAULT-NEXT: Live Stack Slot Analysis
; DEFAULT-NEXT: Greedy Register Allocator
diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll
index f6822713022a9c..cd45fa56f8ecec 100644
--- a/llvm/test/CodeGen/ARM/O3-pipeline.ll
+++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll
@@ -105,6 +105,7 @@
; CHECK-NEXT: Live Interval Analysis
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Modulo Software Pipelining
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction
diff --git a/llvm/test/CodeGen/LoongArch/opt-pipeline.ll b/llvm/test/CodeGen/LoongArch/opt-pipeline.ll
index da26e9846301a1..59bbb3995fa871 100644
--- a/llvm/test/CodeGen/LoongArch/opt-pipeline.ll
+++ b/llvm/test/CodeGen/LoongArch/opt-pipeline.ll
@@ -118,6 +118,7 @@
; LAXX-NEXT: MachineDominator Tree Construction
; LAXX-NEXT: Slot index numbering
; LAXX-NEXT: Live Interval Analysis
+; LAXX-NEXT: Machine Register Class Info Analysis
; LAXX-NEXT: Register Coalescer
; LAXX-NEXT: Rename Disconnected Subregister Components
; LAXX-NEXT: Machine Instruction Scheduler
diff --git a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
index 64325ec772459d..4c1c74367a31a4 100644
--- a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
+++ b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
@@ -113,6 +113,7 @@
; CHECK-NEXT: Machine Trace Metrics
; CHECK-NEXT: Early If-Conversion
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Machine InstCombiner
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: Early Machine Loop Invariant Code Motion
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index b0c756e26985bb..540d9bfae49209 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -115,6 +115,7 @@
; CHECK-NEXT: Remove dead machine instructions
; CHECK-NEXT: Machine Trace Metrics
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Machine InstCombiner
; RV64-NEXT: RISC-V Optimize W Instructions
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
diff --git a/llvm/test/CodeGen/X86/opt-pipeline.ll b/llvm/test/CodeGen/X86/opt-pipeline.ll
index 1bca1b960edda4..8388d768bb2bbb 100644
--- a/llvm/test/CodeGen/X86/opt-pipeline.ll
+++ b/llvm/test/CodeGen/X86/opt-pipeline.ll
@@ -103,6 +103,7 @@
; CHECK-NEXT: Machine Trace Metrics
; CHECK-NEXT: Early If-Conversion
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Machine InstCombiner
; CHECK-NEXT: X86 cmov Conversion
; CHECK-NEXT: MachineDominator Tree Construction
@@ -114,6 +115,7 @@
; CHECK-NEXT: Machine Common Subexpression Elimination
; CHECK-NEXT: MachinePostDominator Tree Construction
; CHECK-NEXT: Machine Cycle Info Analysis
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Machine code sinking
; CHECK-NEXT: Peephole Optimizations
; CHECK-NEXT: Remove dead machine instructions
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