[llvm] [AMDGPU] Fix unreachable reg bit width (PR #122107)

[via llvm-commits]

https://github.com/Shoreshen updated https://github.com/llvm/llvm-project/pull/122107

>From cfbc8ad326557983151dd527270ab807c7139767 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Wed, 8 Jan 2025 21:16:23 +0800
Subject: [PATCH 1/2] fix unreachable reg bit width. need add test case latter

---
 llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 319ada3b27bd5a..d9c0aa300855fc 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2487,6 +2487,7 @@ unsigned getRegBitWidth(unsigned RCID) {
   case AMDGPU::AReg_128_Align2RegClassID:
   case AMDGPU::AV_128RegClassID:
   case AMDGPU::AV_128_Align2RegClassID:
+  case AMDGPU::SReg_128_XNULLRegClassID:
     return 128;
   case AMDGPU::SGPR_160RegClassID:
   case AMDGPU::SReg_160RegClassID:
@@ -2523,6 +2524,7 @@ unsigned getRegBitWidth(unsigned RCID) {
   case AMDGPU::AReg_256_Align2RegClassID:
   case AMDGPU::AV_256RegClassID:
   case AMDGPU::AV_256_Align2RegClassID:
+  case AMDGPU::SReg_256_XNULLRegClassID:
     return 256;
   case AMDGPU::SGPR_288RegClassID:
   case AMDGPU::SReg_288RegClassID:

>From 163fcc1946713cb89574679cfc68c45779b89483 Mon Sep 17 00:00:00 2001
From: ShoreShen <372660931 at qq.com>
Date: Fri, 10 Jan 2025 17:40:21 +0800
Subject: [PATCH 2/2] add test case, hard to find case forind case for
 SReg_128_XNULL & merge main

---
 .../CodeGen/AMDGPU/add-xnull-regclass-bitwidth.mir   | 12 ++++++++++++
 llvm/test/lit.cfg.py                                 |  2 +-
 2 files changed, 13 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/add-xnull-regclass-bitwidth.mir

diff --git a/llvm/test/CodeGen/AMDGPU/add-xnull-regclass-bitwidth.mir b/llvm/test/CodeGen/AMDGPU/add-xnull-regclass-bitwidth.mir
new file mode 100644
index 00000000000000..7c14dc980acfd2
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/add-xnull-regclass-bitwidth.mir
@@ -0,0 +1,12 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=early-machinelicm -run-pass=postmisched -o - %s | FileCheck %s
+---
+name:            test_xnull_256
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_xnull_256
+    ; CHECK: IMAGE_STORE_V4_V2_gfx90a $vgpr0_vgpr1_vgpr2_vgpr3, killed $vgpr8_vgpr9, killed $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, 15, -1, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), addrspace 8)
+    ; CHECK-NEXT: $vgpr2 = V_LSHRREV_B32_e32 4, killed $vgpr2, implicit $exec
+  IMAGE_STORE_V4_V2_gfx90a $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr8_vgpr9, $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, 15, -1, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s128), addrspace 8)
+  $vgpr2 = V_LSHRREV_B32_e32 4, $vgpr2, implicit $exec
+...
diff --git a/llvm/test/lit.cfg.py b/llvm/test/lit.cfg.py
index 5a03a85386e0aa..9839f823ac9f41 100644
--- a/llvm/test/lit.cfg.py
+++ b/llvm/test/lit.cfg.py
@@ -463,7 +463,7 @@ def have_cxx_shared_library():
         print("could not exec llvm-readobj")
         return False
 
-    readobj_out = readobj_cmd.stdout.read().decode("ascii")
+    readobj_out = readobj_cmd.stdout.read().decode("utf-8")
     readobj_cmd.wait()
 
     regex = re.compile(r"(libc\+\+|libstdc\+\+|msvcp).*\.(so|dylib|dll)")