[llvm] [CodeGen][Spill2Reg] Initial patch (PR #118832)

[via llvm-commits]

vporpo wrote:

>> I'd like to ensure this patch doesn't get too focussed on just working for gpr->vector spills. In my experience those profitable cases are pretty rare. What has been more useful has been cases such as storing scalar f32/f64 in the upper elements of xmm registers, or even using ymm upper halfs to store xmm vector data, and to a lesser extent storing a i32 in the upper 32-bits of a i64 gpr.

> Yes, we also observed some cases in which spilling float value into GPR can help performance (suppose GPR register pressure is low meanwhile).

I think that the structure of the pass is already fairly agnostic to the variant of spill2reg (like GPR->lower vector, GPR->upper vector, GPR->upper GPR, F32/64->upper vector). The candidates are filtered by `TRI` callbacks, like `isLegalToSpillToReg()` and code generation is done with `TII` callbacks: `spill2RegInsertToVectorReg()` and `spill2RegExtractFromVectoReg()`. All of these can be update to work with different spill2reg variants.

Once we add support for more than one spill2reg variant, then during the collection phase we would need to determine the variant and set it in `StackSlotDataEntry` using an enum. This is going to be used later in the pass (in `generateCode()`) to generate the corresponding code.

https://github.com/llvm/llvm-project/pull/118832