[llvm] [IA][RISCV] Support VP intrinsics in InterleavedAccessPass (PR #120490)

[Min-Yih Hsu via llvm-commits]

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@@ -248,6 +249,196 @@ static bool isReInterleaveMask(ShuffleVectorInst *SVI, unsigned &Factor,
   return false;
 }
 
+// For an (de)interleave tree like this:
+//
+//   A   C B   D
+//   |___| |___|
+//     |_____|
+//        |
+//     A B C D
+//
+//  We will get ABCD at the end while the leaf operands/results
+//  are ACBD, which are also what we initially collected in
+//  getVectorInterleaveFactor / getVectorDeinterleaveFactor. But TLI
+//  hooks (e.g. lowerInterleavedScalableLoad) expect ABCD, so we need
+//  to reorder them by interleaving these values.
+static void interleaveLeafValues(SmallVectorImpl<Value *> &Leaves) {
+  unsigned Factor = Leaves.size();
+  assert(isPowerOf2_32(Factor) && Factor <= 8 && Factor > 1);
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mshockwave wrote:

> or your current approach but with support to all power_of_2 factors.
> so making it generic for all power_of_2 factors would be better.

Oh yeah absolutely, I added `Factor <= 8` here simply because RISC-V (and I believe AArch64?) support at most 8. But that said, I'm happy to relax this restriction, in which case I literally only need to remove this condition and it should support all power-of-two out of the box.

https://github.com/llvm/llvm-project/pull/120490