[llvm] [MachinePipeliner] Improve loop carried dependence analysis (PR #94185)

[Yuta Mukai via llvm-commits]

================
@@ -1,14 +1,15 @@
 # RUN: llc -mtriple=hexagon -run-pass pipeliner -debug-only=pipeliner %s -o /dev/null 2>&1 -pipeliner-experimental-cg=true | FileCheck %s
 # REQUIRES: asserts
 
-# Test that the loop carried dependence check correctly identifies a recurrence
+# Test that it correctly recognizes that there is no loop carried dependence
----------------
ytmukai wrote:

In this test, the load preceds the store as follows: 

```
%4:intregs = L2_loadri_io %0, -8 :: (load (s32) from %ir.cgep)
S2_storeri_io %0, 0, %12 :: (store (s32) into %ir.lsr.iv1)
%6:intregs = A2_addi %0, -4

# CHECK-NEXT: BaseMI:   S2_storeri_io %{{[0-9]+}}:intregs, 0, %{{[0-9]+}}:intregs :: (store (s32) into %ir.lsr.iv1)
# CHECK-NEXT:   Base + 0 + I * -4, Len: 4
# CHECK-NEXT: OtherMI:   %{{[0-9]+}}:intregs = L2_loadri_io %{{[0-9]+}}:intregs, -8 :: (load (s32) from %ir.cgep)
# CHECK-NEXT:   Base + -8 + I * -4, Len: 4
 ```

iteration 0 : load from X-8
store to X
iteration 1 : load from X-12
store to X-4
iteration 2 : load from X-16
store to X-8

So there should be no loop carried dependence from store to load.

I checked on the other cases.
If the direction of access is reversed as follows, it is correctly detected as having a dependence.

```
- %6:intregs = A2_addi %0, -4
+ %6:intregs = A2_addi %0, 4
```

```
  BaseMI:   S2_storeri_io %2:intregs, 0, %7:intregs :: (store (s32) into %ir.lsr.iv1)
    Base + 0 + I * 4, Len: 4
  OtherMI:   %5:intregs = L2_loadri_io %2:intregs, -8 :: (load (s32) from %ir.cgep)
    Base + -8 + I * 4, Len: 4
  Result: Overlap
```

However, if the offset of the load is changed so that the store precedes it, the dependence is not detected.

```
- %4:intregs = L2_loadri_io %0, -8 :: (load (s32) from %ir.cgep)
+ %4:intregs = L2_loadri_io %0, 8 :: (load (s32) from %ir.cgep)
```

This is because the following code, a decision prior to the part changed in this patch, does not consider access in the negative direction. This should be fixed by #121907.

https://github.com/llvm/llvm-project/blob/dfa5ee2af27da2eee835560bd1f1c872991a558d/llvm/lib/CodeGen/MachinePipeliner.cpp#L877-L879

Tests for other cases were added at `swp-carried-dep5.mir`.

https://github.com/llvm/llvm-project/pull/94185