[llvm] [RISCV][VLOPT] Add getOperandInfo for integer and floating point widening reductions (PR #122176)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 9 06:34:46 PST 2025
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/122176
>From 3e468646943b79262b9cecf02a295763165b44c8 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 8 Jan 2025 13:56:37 -0800
Subject: [PATCH 1/2] [RISCV][VLOPT] Add getOperandInfo for integer and
floating point widening reductions
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 16 ++++++
.../test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 51 +++++++++++++++++++
2 files changed, 67 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index ad61a77df90573..1ff5e01256379f 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -710,6 +710,22 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
return MILog2SEW;
}
+ // Vector Widening Integer Reduction Instructions
+ // The Dest and VS1 read only element 0 for the vector register. Return 2*EEW
+ // for these. VS2 has EEW=SEW and EMUL=LMUL.
+ case RISCV::VWREDSUM_VS:
+ case RISCV::VWREDSUMU_VS:
+ // Vector Widening Floating-Point Reduction Instructions
+ case RISCV::VFWREDOSUM_VS:
+ case RISCV::VFWREDUSUM_VS: {
+ bool TwoTimes = IsMODef || MO.getOperandNo() == 3;
+ unsigned Log2EEW = TwoTimes ? MILog2SEW + 1 : MILog2SEW;
+ if (MO.getOperandNo() == 2)
+ return OperandInfo(
+ RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(Log2EEW, MI), Log2EEW);
+ return OperandInfo(Log2EEW);
+ }
+
default:
return std::nullopt;
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index c4a38345461038..28f711c6c1cf8c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -1224,6 +1224,7 @@ body: |
%x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0
%y:vr = PseudoVIOTA_M_MF2 $noreg, %x, 1, 3 /* e8 */, 0
...
+---
name: vred_vs2
body: |
bb.0:
@@ -1337,3 +1338,53 @@ body: |
%y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
%z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2, 3 /* e8 */, 0
...
+---
+name: vwred_vs2
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vred_vs2
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
+ %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
+...
+---
+name: vwred_vs1
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vwred_vs1
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
+...
+---
+name: vwred_vs1_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vwred_vs1_incompatible_eew
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
+ %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
+...
+---
+name: vwred_vs2_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vwred_vs2_incompatible_eew
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
+...
+---
+name: vwred_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vwred_vs1_incompatible_emul
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
+ %y:vr = PseudoVWREDSUM_VS_MF2_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
+...
>From 94187bfb5dd5eb91baa0e3ee174111c8aa8faee2 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 9 Jan 2025 06:31:22 -0800
Subject: [PATCH 2/2] fixup! fix after rebase
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 15 +++++++++------
llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 8 ++++----
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 1ff5e01256379f..61f8fdcb100c4d 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -711,8 +711,8 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
}
// Vector Widening Integer Reduction Instructions
- // The Dest and VS1 read only element 0 for the vector register. Return 2*EEW
- // for these. VS2 has EEW=SEW and EMUL=LMUL.
+ // The Dest and VS1 read only element 0 for the vector register. Return
+ // 2*EEW for these. VS2 has EEW=SEW and EMUL=LMUL.
case RISCV::VWREDSUM_VS:
case RISCV::VWREDSUMU_VS:
// Vector Widening Floating-Point Reduction Instructions
@@ -720,10 +720,7 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
case RISCV::VFWREDUSUM_VS: {
bool TwoTimes = IsMODef || MO.getOperandNo() == 3;
unsigned Log2EEW = TwoTimes ? MILog2SEW + 1 : MILog2SEW;
- if (MO.getOperandNo() == 2)
- return OperandInfo(
- RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(Log2EEW, MI), Log2EEW);
- return OperandInfo(Log2EEW);
+ return Log2EEW;
}
default:
@@ -745,6 +742,8 @@ getOperandInfo(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
switch (RVV->BaseInstr) {
// Vector Reduction Operations
// Vector Single-Width Integer Reduction Instructions
+ // Vector Widening Integer Reduction Instructions
+ // Vector Widening Floating-Point Reduction Instructions
// The Dest and VS1 only read element 0 of the vector register. Return just
// the EEW for these.
case RISCV::VREDAND_VS:
@@ -755,6 +754,10 @@ getOperandInfo(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
case RISCV::VREDOR_VS:
case RISCV::VREDSUM_VS:
case RISCV::VREDXOR_VS:
+ case RISCV::VWREDSUM_VS:
+ case RISCV::VWREDSUMU_VS:
+ case RISCV::VFWREDOSUM_VS:
+ case RISCV::VFWREDUSUM_VS:
if (MO.getOperandNo() != 2)
return OperandInfo(*Log2EEW);
break;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 28f711c6c1cf8c..df2d1e29ee2842 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -1342,9 +1342,9 @@ body: |
name: vwred_vs2
body: |
bb.0:
- ; CHECK-LABEL: name: vred_vs2
- ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
- ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-LABEL: name: vwred_vs2
+ ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
%y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
...
@@ -1382,7 +1382,7 @@ body: |
name: vwred_incompatible_emul
body: |
bb.0:
- ; CHECK-LABEL: name: vwred_vs1_incompatible_emul
+ ; CHECK-LABEL: name: vwred_incompatible_emul
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
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