[llvm] [RISCV] Fold vector shift of sext/zext to widening multiply (PR #121563)

[Piotr Fusik via llvm-commits]

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@@ -238,12 +238,20 @@ define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b
 }
 
 define <vscale x 2 x i64> @vwsll_vi_nxv2i64(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
-; CHECK-LABEL: vwsll_vi_nxv2i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT:    vzext.vf2 v10, v8
-; CHECK-NEXT:    vsll.vi v8, v10, 2, v0.t
-; CHECK-NEXT:    ret
+; CHECK-RV32-LABEL: vwsll_vi_nxv2i64:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
+; CHECK-RV32-NEXT:    vzext.vf2 v10, v8
+; CHECK-RV32-NEXT:    vsll.vi v8, v10, 2, v0.t
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pfusik wrote:

Done. `combineOp_VLToVWOp_VL` handles `RISCVISD::VMV_V_X_VL` in `AfterLegalizeDAG` instead of `ISD::SPLAT_VECTOR_PARTS` in `AfterLegalizeTypes`. I do the same, so that `vwsll` has priority over `vwmulu`.

https://github.com/llvm/llvm-project/pull/121563