[llvm] [AArch64] Combine and and lsl into ubfiz (PR #118974)

[David Sherwood via llvm-commits]

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@@ -26365,6 +26367,43 @@ performScalarToVectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   return NVCAST;
 }
 
+/// If the operand is a bitwise AND with a constant RHS, and the shift has a
+/// constant RHS and is the only use, we can pull it out of the shift, i.e.
+///
+///   (shl (and X, C1), C2) -> (and (shl X, C2), (shl C1, C2))
+///
+/// We prefer this canonical form to match existing isel patterns.
+static SDValue performSHLCombine(SDNode *N,
+                                 TargetLowering::DAGCombinerInfo &DCI,
+                                 SelectionDAG &DAG) {
+  if (DCI.isBeforeLegalizeOps())
+    return SDValue();
+
+  SDValue Op0 = N->getOperand(0);
+  if (!Op0.hasOneUse() || Op0.getOpcode() != ISD::AND)
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david-arm wrote:

nit: Might be a good idea to check for the AND opcode first, since this is cheaper than checking for one use and should eliminate a lot of cases.

https://github.com/llvm/llvm-project/pull/118974