[llvm] [AArch64] Combine and and lsl into ubfiz (PR #118974)

[David Sherwood via llvm-commits]

================
@@ -26057,6 +26059,41 @@ performScalarToVectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   return NVCAST;
 }
 
+/// If the operand is a bitwise AND with a constant RHS, and the shift has a
+/// constant RHS and is the only use, we can pull it out of the shift, i.e.
+///
+///   (shl (and X, C1), C2) -> (and (shl X, C2), (shl C1, C2))
+///
+/// We prefer this canonical form to match existing isel patterns.
+static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG) {
+  EVT VT = N->getValueType(0);
+  if (VT != MVT::i32 && VT != MVT::i64)
----------------
david-arm wrote:

It looks like we're doing this to avoid worrying about legalisation of MVT::i16 and MVT::i8 types. However, instead we might be able to just write:

```
  if (DCI.isBeforeLegalizeOps())
    return SDValue();
```

This way we know that at the time of doing the canonicalisation all integer types are guaranteed to be i32 or i64. It also ensures consistency because otherwise we're doing the combine at different times for different types.

https://github.com/llvm/llvm-project/pull/118974