[llvm] Fix unreachable reg bit width (PR #122107)

[via llvm-commits]

https://github.com/Shoreshen created https://github.com/llvm/llvm-project/pull/122107

Add register class bit width for SReg_256_XNULL and SReg_128_XNULL

>From cfbc8ad326557983151dd527270ab807c7139767 Mon Sep 17 00:00:00 2001
From: shore <372660931 at qq.com>
Date: Wed, 8 Jan 2025 21:16:23 +0800
Subject: [PATCH] fix unreachable reg bit width. need add test case latter

---
 llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 319ada3b27bd5a..d9c0aa300855fc 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2487,6 +2487,7 @@ unsigned getRegBitWidth(unsigned RCID) {
   case AMDGPU::AReg_128_Align2RegClassID:
   case AMDGPU::AV_128RegClassID:
   case AMDGPU::AV_128_Align2RegClassID:
+  case AMDGPU::SReg_128_XNULLRegClassID:
     return 128;
   case AMDGPU::SGPR_160RegClassID:
   case AMDGPU::SReg_160RegClassID:
@@ -2523,6 +2524,7 @@ unsigned getRegBitWidth(unsigned RCID) {
   case AMDGPU::AReg_256_Align2RegClassID:
   case AMDGPU::AV_256RegClassID:
   case AMDGPU::AV_256_Align2RegClassID:
+  case AMDGPU::SReg_256_XNULLRegClassID:
     return 256;
   case AMDGPU::SGPR_288RegClassID:
   case AMDGPU::SReg_288RegClassID: