[llvm] [RISCV][VLOpt] Consolidate EMUL=SEW/EEW*LMUL logic [NFC] (PR #122021)

[Luke Lau via llvm-commits]

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@@ -721,16 +708,48 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
   case RISCV::VREDOR_VS:
   case RISCV::VREDSUM_VS:
   case RISCV::VREDXOR_VS: {
-    if (MO.getOperandNo() == 2)
-      return OperandInfo(MIVLMul, MILog2SEW);
-    return OperandInfo(MILog2SEW);
+    return MILog2SEW;
   }
 
   default:
     return {};
   }
 }
 
+static OperandInfo getOperandInfo(const MachineOperand &MO,
+                                  const MachineRegisterInfo *MRI) {
+  const MachineInstr &MI = *MO.getParent();
+  const RISCVVPseudosTable::PseudoInfo *RVV =
+      RISCVVPseudosTable::getPseudoInfo(MI.getOpcode());
+  assert(RVV && "Could not find MI in PseudoTable");
+
+  std::optional<unsigned> Log2EEW = getOperandLog2EEW(MO, MRI);
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lukel97 wrote:

Just an observation, it's a shame we have to do another pseudo table lookup. We could plumb `RVV->BaseInstr` through to `getOperandLog2EEW` but that introduces an invariant. 

https://github.com/llvm/llvm-project/pull/122021