[llvm] [RISCV][VLOPT] Add mask load to isSupported and getOperandInfo (PR #122030)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 7 18:21:05 PST 2025
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@@ -257,6 +257,9 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
// Vector Unit-Stride Instructions
// Vector Strided Instructions
/// Dest EEW encoded in the instruction and EMUL=(EEW/SEW)*LMUL
+ case RISCV::VLM_V:
+ case RISCV::VSM_V:
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michaelmaitland wrote:
Added, although I'm not sure that it makes sense to have an incompatible_eew test does it?
https://github.com/llvm/llvm-project/pull/122030
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