[llvm] 51c9c82 - [RISCV] Added test case for PR119527. NFC (#121816)

[via llvm-commits]

Author: Mikhail R. Gadelha
Date: 2025-01-07T13:33:22-03:00
New Revision: 51c9c823ca187895478e42883ba7a8d1f3150e87

URL: https://github.com/llvm/llvm-project/commit/51c9c823ca187895478e42883ba7a8d1f3150e87
DIFF: https://github.com/llvm/llvm-project/commit/51c9c823ca187895478e42883ba7a8d1f3150e87.diff

LOG: [RISCV] Added test case for PR119527. NFC (#121816)

Co-authored-by: Luke Lau <luke_lau at icloud.com>

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
index fe89b4aa24171c..d7f62ae8343469 100644
--- a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
+++ b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
@@ -320,6 +320,19 @@ define i64 @add_shl_moreOneUse_sh3add(i64 %x) {
   ret i64 %add
 }
 
+;; Covers a case which previously crashed (pr119527)
+define i64 @add_shl_sext(i32 %1) {
+; RV64-LABEL: add_shl_sext:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a1, a0, 3
+; RV64-NEXT:    sllw a0, a1, a0
+; RV64-NEXT:    ret
+  %3 = add i32 %1, 3
+  %4 = shl i32 %3, %1
+  %5 = sext i32 %4 to i64
+  ret i64 %5
+}
+
 define i64 @add_shl_moreOneUse_sh4add(i64 %x) {
 ; RV64-LABEL: add_shl_moreOneUse_sh4add:
 ; RV64:       # %bb.0: