[llvm] [LoopInterchange] Bail out for Scalar Dependencies (PR #119345)
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 7 08:05:35 PST 2025
https://github.com/sjoerdmeijer updated https://github.com/llvm/llvm-project/pull/119345
>From dae2cad7639c1933fa45f3160b0aed9e5bfbe601 Mon Sep 17 00:00:00 2001
From: Sjoerd Meijer <smeijer at nvidia.com>
Date: Thu, 21 Nov 2024 07:07:20 -0800
Subject: [PATCH] [LoopInterchange] Bail out for Scalar Dependencies
We are not handling 'S' scalar dependencies correctly and have at least
the following miscompiles related to that:
[LoopInterchange] incorrect handling of scalar dependencies and dependence vectors starting with ">" #54176
[LoopInterchange] Interchange breaks program correctness #46867
[LoopInterchange] Loops should not interchanged due to dependencies #47259
[LoopInterchange] Loops should not interchanged due to control flow #47401
This patch checks that the dependency matrix has no "S" direction as the
leftmost non-"=" direction in any row. This is a stopgap that prevents
the miscompiles, at the expense of handling less cases, i.e. making
interchange more pessimistic. However, some of the cases that are now
rejected for dependence analysis reasons, were rejected before for other
reasons (e.g. profitability). So at least for the llvm regression tests,
the number of regression are very reasonable.
This should be a stopgap. We would like to get interchange enabled by
default and thus prefer correctness over unsafe transforms, and later
lift this restriction.
---
.../lib/Transforms/Scalar/LoopInterchange.cpp | 5 +
.../LoopInterchange/gh54176-scalar-deps.ll | 44 ++-----
.../LoopInterchange/inner-only-reductions.ll | 4 +-
...most-latch-uses-values-in-middle-header.ll | 25 ++--
.../interchange-flow-dep-outer.ll | 18 +--
llvm/test/Transforms/LoopInterchange/lcssa.ll | 4 +-
.../outer-header-jump-to-inner-latch.ll | 120 ++++++++----------
.../pr43176-move-to-new-latch.ll | 8 +-
...97-lcssa-for-multiple-outer-loop-blocks.ll | 52 +++-----
.../LoopInterchange/profitability.ll | 20 +--
.../reductions-across-inner-and-outer-loop.ll | 2 +-
.../LoopInterchange/vector-gep-operand.ll | 16 +--
12 files changed, 117 insertions(+), 201 deletions(-)
diff --git a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
index a0c0080c0bda1c..059aff7e88a699 100644
--- a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
@@ -188,6 +188,11 @@ static void interChangeDependencies(CharMatrix &DepMatrix, unsigned FromIndx,
// columns, has no ">" direction as the leftmost non-"=" direction in any row.
static bool isLexicographicallyPositive(std::vector<char> &DV) {
for (unsigned char Direction : DV) {
+ // FIXME: we reject scalar dependencies because we currently don't
+ // handle them correctly. This makes the legality check more conservative
+ // than needed, but is a stopgap to avoid miscompiles.
+ if (Direction == 'S')
+ return false;
if (Direction == '<')
return true;
if (Direction == '>' || Direction == '*')
diff --git a/llvm/test/Transforms/LoopInterchange/gh54176-scalar-deps.ll b/llvm/test/Transforms/LoopInterchange/gh54176-scalar-deps.ll
index b3383655668980..2168cde7f5374b 100644
--- a/llvm/test/Transforms/LoopInterchange/gh54176-scalar-deps.ll
+++ b/llvm/test/Transforms/LoopInterchange/gh54176-scalar-deps.ll
@@ -29,19 +29,13 @@
define dso_local i32 @test1(i1 %cond) {
; CHECK-LABEL: define dso_local i32 @test1(
; CHECK-SAME: i1 [[COND:%.*]]) {
-; CHECK-NEXT: [[FOR_PREHEADER:.*:]]
-; CHECK-NEXT: br label %[[INNERLOOP_PREHEADER:.*]]
-; CHECK: [[OUTERLOOP_PREHEADER:.*]]:
+; CHECK-NEXT: [[FOR_PREHEADER:.*]]:
; CHECK-NEXT: br label %[[OUTERLOOP:.*]]
; CHECK: [[OUTERLOOP]]:
-; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[INDVARS_IV_NEXT21_I:%.*]], %[[FOR_LATCH:.*]] ], [ 0, %[[OUTERLOOP_PREHEADER]] ]
-; CHECK-NEXT: br label %[[INNERLOOP_SPLIT:.*]]
-; CHECK: [[INNERLOOP_PREHEADER]]:
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[FOR_PREHEADER]] ], [ [[INDVARS_IV_NEXT21_I:%.*]], %[[FOR_LATCH:.*]] ]
; CHECK-NEXT: br label %[[INNERLOOP:.*]]
; CHECK: [[INNERLOOP]]:
-; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[TMP0:%.*]], %[[IF_END_SPLIT:.*]] ], [ 0, %[[INNERLOOP_PREHEADER]] ]
-; CHECK-NEXT: br label %[[OUTERLOOP_PREHEADER]]
-; CHECK: [[INNERLOOP_SPLIT]]:
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ 0, %[[OUTERLOOP]] ], [ [[TMP0:%.*]], %[[IF_END:.*]] ]
; CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [4 x [9 x i32]], ptr @f, i64 0, i64 [[J]], i64 [[I]]
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[ARRAYIDX6_I]], align 4
; CHECK-NEXT: [[TOBOOL_I:%.*]] = icmp eq i32 [[I1]], 0
@@ -50,24 +44,20 @@ define dso_local i32 @test1(i1 %cond) {
; CHECK-NEXT: store i32 3, ptr @g, align 4
; CHECK-NEXT: br label %[[LAND_END]]
; CHECK: [[LAND_END]]:
-; CHECK-NEXT: br i1 [[COND]], label %[[IF_END:.*]], label %[[IF_THEN:.*]]
+; CHECK-NEXT: br i1 [[COND]], label %[[IF_END]], label %[[IF_THEN:.*]]
; CHECK: [[IF_THEN]]:
; CHECK-NEXT: [[I2:%.*]] = load i32, ptr @g, align 4
; CHECK-NEXT: [[INC_I:%.*]] = add i32 [[I2]], 1
; CHECK-NEXT: store i32 [[INC_I]], ptr @g, align 4
; CHECK-NEXT: br label %[[IF_END]]
; CHECK: [[IF_END]]:
-; CHECK-NEXT: [[J_NEXT:%.*]] = add nuw nsw i64 [[J]], 1
-; CHECK-NEXT: [[EXITCOND_I:%.*]] = icmp eq i64 [[J_NEXT]], 3
-; CHECK-NEXT: br label %[[FOR_LATCH]]
-; CHECK: [[IF_END_SPLIT]]:
; CHECK-NEXT: [[TMP0]] = add nuw nsw i64 [[J]], 1
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[EXIT:.*]], label %[[INNERLOOP]]
+; CHECK-NEXT: br i1 [[TMP1]], label %[[FOR_LATCH]], label %[[INNERLOOP]]
; CHECK: [[FOR_LATCH]]:
; CHECK-NEXT: [[INDVARS_IV_NEXT21_I]] = add nsw i64 [[I]], 1
; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i64 [[I]], 2
-; CHECK-NEXT: br i1 [[CMP_I]], label %[[OUTERLOOP]], label %[[IF_END_SPLIT]]
+; CHECK-NEXT: br i1 [[CMP_I]], label %[[OUTERLOOP]], label %[[EXIT:.*]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[I3:%.*]] = load i32, ptr @g, align 4
; CHECK-NEXT: ret i32 [[I3]]
@@ -139,19 +129,13 @@ exit:
define dso_local i32 @test2(i1 %cond) {
; CHECK-LABEL: define dso_local i32 @test2(
; CHECK-SAME: i1 [[COND:%.*]]) {
-; CHECK-NEXT: [[FOR_PREHEADER:.*:]]
-; CHECK-NEXT: br label %[[INNERLOOP_PREHEADER:.*]]
-; CHECK: [[OUTERLOOP_PREHEADER:.*]]:
+; CHECK-NEXT: [[FOR_PREHEADER:.*]]:
; CHECK-NEXT: br label %[[OUTERLOOP:.*]]
; CHECK: [[OUTERLOOP]]:
-; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[INDVARS_IV_NEXT21_I:%.*]], %[[FOR_LATCH:.*]] ], [ 0, %[[OUTERLOOP_PREHEADER]] ]
-; CHECK-NEXT: br label %[[INNERLOOP_SPLIT:.*]]
-; CHECK: [[INNERLOOP_PREHEADER]]:
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[FOR_PREHEADER]] ], [ [[INDVARS_IV_NEXT21_I:%.*]], %[[FOR_LATCH:.*]] ]
; CHECK-NEXT: br label %[[INNERLOOP:.*]]
; CHECK: [[INNERLOOP]]:
-; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[TMP0:%.*]], %[[IF_END_SPLIT:.*]] ], [ 0, %[[INNERLOOP_PREHEADER]] ]
-; CHECK-NEXT: br label %[[OUTERLOOP_PREHEADER]]
-; CHECK: [[INNERLOOP_SPLIT]]:
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ 0, %[[OUTERLOOP]] ], [ [[TMP0:%.*]], %[[IF_END:.*]] ]
; CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [4 x [9 x i32]], ptr @f, i64 0, i64 [[J]], i64 [[I]]
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[ARRAYIDX6_I]], align 4
; CHECK-NEXT: [[TOBOOL_I:%.*]] = icmp eq i32 [[I1]], 0
@@ -160,24 +144,20 @@ define dso_local i32 @test2(i1 %cond) {
; CHECK: [[LAND_RHS]]:
; CHECK-NEXT: br label %[[LAND_END]]
; CHECK: [[LAND_END]]:
-; CHECK-NEXT: br i1 [[COND]], label %[[IF_END:.*]], label %[[IF_THEN:.*]]
+; CHECK-NEXT: br i1 [[COND]], label %[[IF_END]], label %[[IF_THEN:.*]]
; CHECK: [[IF_THEN]]:
; CHECK-NEXT: [[I2:%.*]] = load i32, ptr @g, align 4
; CHECK-NEXT: [[INC_I:%.*]] = add i32 [[I2]], 1
; CHECK-NEXT: store i32 [[INC_I]], ptr @g, align 4
; CHECK-NEXT: br label %[[IF_END]]
; CHECK: [[IF_END]]:
-; CHECK-NEXT: [[J_NEXT:%.*]] = add nuw nsw i64 [[J]], 1
-; CHECK-NEXT: [[EXITCOND_I:%.*]] = icmp eq i64 [[J_NEXT]], 3
-; CHECK-NEXT: br label %[[FOR_LATCH]]
-; CHECK: [[IF_END_SPLIT]]:
; CHECK-NEXT: [[TMP0]] = add nuw nsw i64 [[J]], 1
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[EXIT:.*]], label %[[INNERLOOP]]
+; CHECK-NEXT: br i1 [[TMP1]], label %[[FOR_LATCH]], label %[[INNERLOOP]]
; CHECK: [[FOR_LATCH]]:
; CHECK-NEXT: [[INDVARS_IV_NEXT21_I]] = add nsw i64 [[I]], 1
; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i64 [[I]], 2
-; CHECK-NEXT: br i1 [[CMP_I]], label %[[OUTERLOOP]], label %[[IF_END_SPLIT]]
+; CHECK-NEXT: br i1 [[CMP_I]], label %[[OUTERLOOP]], label %[[EXIT:.*]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[I3:%.*]] = load i32, ptr @g, align 4
; CHECK-NEXT: ret i32 [[I3]]
diff --git a/llvm/test/Transforms/LoopInterchange/inner-only-reductions.ll b/llvm/test/Transforms/LoopInterchange/inner-only-reductions.ll
index 79a1cb71169665..ccc80315103a76 100644
--- a/llvm/test/Transforms/LoopInterchange/inner-only-reductions.ll
+++ b/llvm/test/Transforms/LoopInterchange/inner-only-reductions.ll
@@ -18,7 +18,7 @@
; CHECK: --- !Missed
; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: UnsupportedPHI
+; CHECK-NEXT: Name: Dependence
; CHECK-NEXT: Function: reduction_01
; IR-LABEL: @reduction_01(
@@ -71,7 +71,7 @@ for.end8: ; preds = %for.cond1.for.inc6_
; CHECK: --- !Missed
; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: UnsupportedPHIOuter
+; CHECK-NEXT: Name: Dependence
; CHECK-NEXT: Function: reduction_03
; IR-LABEL: @reduction_03(
diff --git a/llvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll b/llvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll
index bad84224d445ab..3057742d8d047f 100644
--- a/llvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll
+++ b/llvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll
@@ -18,35 +18,28 @@ define void @innermost_latch_uses_values_in_middle_header() {
; CHECK: [[OUTERMOST_HEADER]]:
; CHECK-NEXT: [[INDVAR_OUTERMOST:%.*]] = phi i32 [ 10, %[[ENTRY]] ], [ [[INDVAR_OUTERMOST_NEXT:%.*]], %[[OUTERMOST_LATCH:.*]] ]
; CHECK-NEXT: [[TOBOOL71_I:%.*]] = icmp eq i32 [[TMP0]], 0
-; CHECK-NEXT: br i1 [[TOBOOL71_I]], label %[[INNERMOST_HEADER_PREHEADER:.*]], label %[[OUTERMOST_LATCH]]
-; CHECK: [[MIDDLE_HEADER_PREHEADER:.*]]:
+; CHECK-NEXT: br i1 [[TOBOOL71_I]], label %[[MIDDLE_HEADER_PREHEADER:.*]], label %[[OUTERMOST_LATCH]]
+; CHECK: [[MIDDLE_HEADER_PREHEADER]]:
; CHECK-NEXT: br label %[[MIDDLE_HEADER:.*]]
; CHECK: [[MIDDLE_HEADER]]:
; CHECK-NEXT: [[INDVAR_MIDDLE:%.*]] = phi i64 [ [[INDVAR_MIDDLE_NEXT:%.*]], %[[MIDDLE_LATCH:.*]] ], [ 4, %[[MIDDLE_HEADER_PREHEADER]] ]
; CHECK-NEXT: [[INDVAR_MIDDLE_WIDE:%.*]] = zext i32 [[B]] to i64
-; CHECK-NEXT: br label %[[INNERMOST_BODY:.*]]
-; CHECK: [[INNERMOST_HEADER_PREHEADER]]:
; CHECK-NEXT: br label %[[INNERMOST_HEADER:.*]]
; CHECK: [[INNERMOST_HEADER]]:
-; CHECK-NEXT: [[INDVAR_INNERMOST:%.*]] = phi i64 [ [[TMP1:%.*]], %[[INNERMOST_LATCH_SPLIT:.*]] ], [ 4, %[[INNERMOST_HEADER_PREHEADER]] ]
-; CHECK-NEXT: br label %[[MIDDLE_HEADER_PREHEADER]]
+; CHECK-NEXT: [[INDVAR_INNERMOST:%.*]] = phi i64 [ [[TMP3:%.*]], %[[INNERMOST_LATCH:.*]] ], [ 4, %[[MIDDLE_HEADER]] ]
+; CHECK-NEXT: br label %[[INNERMOST_BODY:.*]]
; CHECK: [[INNERMOST_BODY]]:
; CHECK-NEXT: [[ARRAYIDX9_I:%.*]] = getelementptr inbounds [1 x [6 x i32]], ptr @d, i64 0, i64 [[INDVAR_INNERMOST]], i64 [[INDVAR_MIDDLE]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX9_I]], align 4
-; CHECK-NEXT: br label %[[INNERMOST_LATCH:.*]]
+; CHECK-NEXT: br label %[[INNERMOST_LATCH]]
; CHECK: [[INNERMOST_LATCH]]:
-; CHECK-NEXT: [[INDVAR_INNERMOST_NEXT:%.*]] = add nsw i64 [[INDVAR_INNERMOST]], 1
-; CHECK-NEXT: [[TOBOOL5_I:%.*]] = icmp eq i64 [[INDVAR_INNERMOST_NEXT]], [[INDVAR_MIDDLE_WIDE]]
-; CHECK-NEXT: br label %[[MIDDLE_LATCH]]
-; CHECK: [[INNERMOST_LATCH_SPLIT]]:
-; CHECK-NEXT: [[INDVAR_MIDDLE_WIDE_LCSSA:%.*]] = phi i64 [ [[INDVAR_MIDDLE_WIDE]], %[[MIDDLE_LATCH]] ]
-; CHECK-NEXT: [[TMP1]] = add nsw i64 [[INDVAR_INNERMOST]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], [[INDVAR_MIDDLE_WIDE_LCSSA]]
-; CHECK-NEXT: br i1 [[TMP2]], label %[[OUTERMOST_LATCH_LOOPEXIT:.*]], label %[[INNERMOST_HEADER]]
+; CHECK-NEXT: [[TMP3]] = add nsw i64 [[INDVAR_INNERMOST]], 1
+; CHECK-NEXT: [[TOBOOL5_I:%.*]] = icmp eq i64 [[TMP3]], [[INDVAR_MIDDLE_WIDE]]
+; CHECK-NEXT: br i1 [[TOBOOL5_I]], label %[[MIDDLE_LATCH]], label %[[INNERMOST_HEADER]]
; CHECK: [[MIDDLE_LATCH]]:
; CHECK-NEXT: [[INDVAR_MIDDLE_NEXT]] = add nsw i64 [[INDVAR_MIDDLE]], -1
; CHECK-NEXT: [[TOBOOL2_I:%.*]] = icmp eq i64 [[INDVAR_MIDDLE_NEXT]], 0
-; CHECK-NEXT: br i1 [[TOBOOL2_I]], label %[[INNERMOST_LATCH_SPLIT]], label %[[MIDDLE_HEADER]]
+; CHECK-NEXT: br i1 [[TOBOOL2_I]], label %[[OUTERMOST_LATCH_LOOPEXIT:.*]], label %[[MIDDLE_HEADER]]
; CHECK: [[OUTERMOST_LATCH_LOOPEXIT]]:
; CHECK-NEXT: br label %[[OUTERMOST_LATCH]]
; CHECK: [[OUTERMOST_LATCH]]:
diff --git a/llvm/test/Transforms/LoopInterchange/interchange-flow-dep-outer.ll b/llvm/test/Transforms/LoopInterchange/interchange-flow-dep-outer.ll
index 6daf61a4ec0075..570fe008f52f1b 100644
--- a/llvm/test/Transforms/LoopInterchange/interchange-flow-dep-outer.ll
+++ b/llvm/test/Transforms/LoopInterchange/interchange-flow-dep-outer.ll
@@ -36,13 +36,9 @@ define void @interchange_09(i32 %k) {
; CHECK-NEXT: [[CALL:%.*]] = call double @fn1()
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x double], ptr @T, i64 0, i64 [[INDVARS_IV45]]
; CHECK-NEXT: store double [[CALL]], ptr [[ARRAYIDX]], align 8
-; CHECK-NEXT: br label %[[FOR_BODY9_PREHEADER:.*]]
-; CHECK: [[FOR_COND6_PREHEADER_PREHEADER:.*]]:
; CHECK-NEXT: br label %[[FOR_COND6_PREHEADER:.*]]
; CHECK: [[FOR_COND6_PREHEADER]]:
-; CHECK-NEXT: [[INDVARS_IV42:%.*]] = phi i64 [ [[INDVARS_IV_NEXT43:%.*]], %[[FOR_COND_CLEANUP8:.*]] ], [ 0, %[[FOR_COND6_PREHEADER_PREHEADER]] ]
-; CHECK-NEXT: br label %[[FOR_BODY9_SPLIT1:.*]]
-; CHECK: [[FOR_BODY9_PREHEADER]]:
+; CHECK-NEXT: [[INDVARS_IV42:%.*]] = phi i64 [ 0, %[[FOR_BODY]] ], [ [[INDVARS_IV_NEXT43:%.*]], %[[FOR_COND_CLEANUP8:.*]] ]
; CHECK-NEXT: br label %[[FOR_BODY9:.*]]
; CHECK: [[FOR_COND_CLEANUP4]]:
; CHECK-NEXT: [[TMP:%.*]] = load double, ptr [[ARRAYIDX]], align 8
@@ -53,23 +49,17 @@ define void @interchange_09(i32 %k) {
; CHECK: [[FOR_COND_CLEANUP8]]:
; CHECK-NEXT: [[INDVARS_IV_NEXT43]] = add nuw nsw i64 [[INDVARS_IV42]], 1
; CHECK-NEXT: [[EXITCOND44:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT43]], 1000
-; CHECK-NEXT: br i1 [[EXITCOND44]], label %[[FOR_COND6_PREHEADER]], label %[[FOR_BODY9_SPLIT:.*]]
+; CHECK-NEXT: br i1 [[EXITCOND44]], label %[[FOR_COND6_PREHEADER]], label %[[FOR_COND_CLEANUP4]]
; CHECK: [[FOR_BODY9]]:
-; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP0:%.*]], %[[FOR_BODY9_SPLIT]] ], [ 1, %[[FOR_BODY9_PREHEADER]] ]
-; CHECK-NEXT: br label %[[FOR_COND6_PREHEADER_PREHEADER]]
-; CHECK: [[FOR_BODY9_SPLIT1]]:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 1, %[[FOR_COND6_PREHEADER]] ], [ [[TMP0:%.*]], %[[FOR_BODY9]] ]
; CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [1000 x [1000 x i32]], ptr @Arr, i64 0, i64 [[INDVARS_IV]], i64 [[INDVARS_IV42]]
; CHECK-NEXT: [[T1:%.*]] = load i32, ptr [[ARRAYIDX13]], align 4
; CHECK-NEXT: [[T2:%.*]] = trunc i64 [[INDVARS_IV45]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[T1]], [[T2]]
; CHECK-NEXT: store i32 [[ADD]], ptr [[ARRAYIDX13]], align 4
-; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], 1000
-; CHECK-NEXT: br label %[[FOR_COND_CLEANUP8]]
-; CHECK: [[FOR_BODY9_SPLIT]]:
; CHECK-NEXT: [[TMP0]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[TMP0]], 1000
-; CHECK-NEXT: br i1 [[TMP1]], label %[[FOR_BODY9]], label %[[FOR_COND_CLEANUP4]]
+; CHECK-NEXT: br i1 [[TMP1]], label %[[FOR_BODY9]], label %[[FOR_COND_CLEANUP8]]
;
entry:
br label %for.body
diff --git a/llvm/test/Transforms/LoopInterchange/lcssa.ll b/llvm/test/Transforms/LoopInterchange/lcssa.ll
index b41eba4ef56173..23db652e9a984d 100644
--- a/llvm/test/Transforms/LoopInterchange/lcssa.ll
+++ b/llvm/test/Transforms/LoopInterchange/lcssa.ll
@@ -177,7 +177,7 @@ for.end16: ; preds = %for.exit
}
; PHI node in inner latch with multiple predecessors.
-; REMARK: Interchanged
+; REMARK: Dependence
; REMARK-NEXT: lcssa_05
define void @lcssa_05(ptr %ptr) {
@@ -222,7 +222,7 @@ for.end16: ; preds = %for.exit
ret void
}
-; REMARK: UnsupportedExitPHI
+; REMARK: Dependence
; REMARK-NEXT: lcssa_06
define void @lcssa_06(ptr %ptr, ptr %ptr1) {
diff --git a/llvm/test/Transforms/LoopInterchange/outer-header-jump-to-inner-latch.ll b/llvm/test/Transforms/LoopInterchange/outer-header-jump-to-inner-latch.ll
index 6db95c09b175f9..91cc7483fd1def 100644
--- a/llvm/test/Transforms/LoopInterchange/outer-header-jump-to-inner-latch.ll
+++ b/llvm/test/Transforms/LoopInterchange/outer-header-jump-to-inner-latch.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=loop-interchange -cache-line-size=64 -verify-dom-info -verify-loop-info -verify-loop-lcssa -S %s | FileCheck %s
@b = global [3 x [5 x [8 x i16]]] [[5 x [8 x i16]] zeroinitializer, [5 x [8 x i16]] [[8 x i16] zeroinitializer, [8 x i16] [i16 0, i16 0, i16 0, i16 6, i16 1, i16 6, i16 0, i16 0], [8 x i16] zeroinitializer, [8 x i16] zeroinitializer, [8 x i16] zeroinitializer], [5 x [8 x i16]] zeroinitializer], align 2
@@ -21,44 +22,37 @@
;; }
define void @test1() {
-;CHECK-LABEL: @test1(
-;CHECK: entry:
-;CHECK-NEXT: br label [[FOR_COND1_PREHEADER:%.*]]
-;CHECK: for.body.preheader:
-;CHECK-NEXT: br label [[FOR_BODY:%.*]]
-;CHECK: for.body:
-;CHECK-NEXT: [[INDVARS_IV22:%.*]] = phi i64 [ [[INDVARS_IV_NEXT23:%.*]], [[FOR_INC8:%.*]] ], [ 0, [[FOR_BODY_PREHEADER:%.*]] ]
-;CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[INDVARS_IV22:%.*]], 0
-;CHECK-NEXT: br i1 [[TOBOOL]], label [[FOR_BODY3_SPLIT1:%.*]], label [[FOR_BODY3_SPLIT:%.*]]
-;CHECK: for.cond1.preheader:
-;CHECK-NEXT: br label [[FOR_BODY3:%.*]]
-;CHECK: for.body3:
-;CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER]] ], [ %3, [[FOR_BODY3_SPLIT]] ]
-;CHECK-NEXT: br label [[FOR_BODY_PREHEADER]]
-;CHECK: for.body3.split1:
-;CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[INDVARS_IV22]], 5
-;CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [3 x [5 x [8 x i16]]], ptr @b, i64 0, i64 [[INDVARS_IV]], i64 [[INDVARS_IV]], i64 [[TMP0]]
-;CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[ARRAYIDX7]]
-;CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
-;CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @a
-;CHECK-NEXT: [[TMP_OR:%.*]] = or i32 [[TMP2]], [[CONV]]
-;CHECK-NEXT: store i32 [[TMP_OR]], ptr @a
-;CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
-;CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], 3
-;CHECK-NEXT: br label [[FOR_INC8_LOOPEXIT:%.*]]
-;CHECK: for.body3.split:
-;CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
-;CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 3
-;CHECK-NEXT: br i1 %4, label [[FOR_BODY3]], label [[FOR_END10:%.*]]
-;CHECK: for.inc8.loopexit:
-;CHECK-NEXT: br label [[FOR_INC8]]
-;CHECK: for.inc8:
-;CHECK-NEXT: [[INDVARS_IV_NEXT23]] = add nuw nsw i64 [[INDVARS_IV22]], 1
-;CHECK-NEXT: [[EXITCOND25:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT23]], 3
-;CHECK-NEXT: br i1 [[EXITCOND25]], label [[FOR_BODY]], label [[FOR_BODY3_SPLIT]]
-;CHECK: for.end10:
-;CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr @a
-;CHECK-NEXT: ret void
+; CHECK-LABEL: define void @test1() {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK: [[FOR_BODY]]:
+; CHECK-NEXT: [[INDVARS_IV22:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDVARS_IV_NEXT23:%.*]], %[[FOR_INC8:.*]] ]
+; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[INDVARS_IV22]], 0
+; CHECK-NEXT: br i1 [[TOBOOL]], label %[[FOR_COND1_PREHEADER:.*]], label %[[FOR_INC8]]
+; CHECK: [[FOR_COND1_PREHEADER]]:
+; CHECK-NEXT: br label %[[FOR_BODY3:.*]]
+; CHECK: [[FOR_BODY3]]:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[FOR_COND1_PREHEADER]] ], [ [[TMP3:%.*]], %[[FOR_BODY3]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[INDVARS_IV22]], 5
+; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [3 x [5 x [8 x i16]]], ptr @b, i64 0, i64 [[INDVARS_IV]], i64 [[INDVARS_IV]], i64 [[TMP0]]
+; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2
+; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @a, align 4
+; CHECK-NEXT: [[TMP_OR:%.*]] = or i32 [[TMP2]], [[CONV]]
+; CHECK-NEXT: store i32 [[TMP_OR]], ptr @a, align 4
+; CHECK-NEXT: [[TMP3]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 3
+; CHECK-NEXT: br i1 [[TMP4]], label %[[FOR_BODY3]], label %[[FOR_INC8_LOOPEXIT:.*]]
+; CHECK: [[FOR_INC8_LOOPEXIT]]:
+; CHECK-NEXT: br label %[[FOR_INC8]]
+; CHECK: [[FOR_INC8]]:
+; CHECK-NEXT: [[INDVARS_IV_NEXT23]] = add nuw nsw i64 [[INDVARS_IV22]], 1
+; CHECK-NEXT: [[EXITCOND25:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT23]], 3
+; CHECK-NEXT: br i1 [[EXITCOND25]], label %[[FOR_BODY]], label %[[FOR_END10:.*]]
+; CHECK: [[FOR_END10]]:
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr @a, align 4
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
@@ -118,45 +112,37 @@ for.end10: ; preds = %for.inc8
;; }
define void @test2() {
-; CHECK-LABEL: @test2(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: br label [[OUTERMOST_HEADER:%.*]]
-; CHECK: outermost.header:
-; CHECK-NEXT: [[INDVAR_OUTERMOST:%.*]] = phi i32 [ 10, [[ENTRY:%.*]] ], [ [[INDVAR_OUTERMOST_NEXT:%.*]], [[OUTERMOST_LATCH:%.*]] ]
+; CHECK-LABEL: define void @test2() {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[OUTERMOST_HEADER:.*]]
+; CHECK: [[OUTERMOST_HEADER]]:
+; CHECK-NEXT: [[INDVAR_OUTERMOST:%.*]] = phi i32 [ 10, %[[ENTRY]] ], [ [[INDVAR_OUTERMOST_NEXT:%.*]], %[[OUTERMOST_LATCH:.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4
; CHECK-NEXT: [[TOBOOL71_I:%.*]] = icmp eq i32 [[TMP0]], 0
-; CHECK-NEXT: br label [[INNERMOST_PREHEADER:%.*]]
-; CHECK: middle.header.preheader:
-; CHECK-NEXT: br label [[MIDDLE_HEADER:%.*]]
-; CHECK: middle.header:
-; CHECK-NEXT: [[INDVAR_MIDDLE:%.*]] = phi i64 [ [[INDVAR_MIDDLE_NEXT:%.*]], [[MIDDLE_LATCH:%.*]] ], [ 4, [[MIDDLE_HEADER_PREHEADER:%.*]] ]
-; CHECK-NEXT: br i1 [[TOBOOL71_I]], label [[INNERMOST_BODY_SPLIT1:%.*]], label [[INNERMOST_BODY_SPLIT:%.*]]
-; CHECK: innermost.preheader:
-; CHECK-NEXT: br label [[INNERMOST_BODY:%.*]]
-; CHECK: innermost.body:
-; CHECK-NEXT: [[INDVAR_INNERMOST:%.*]] = phi i64 [ [[TMP1:%.*]], [[INNERMOST_BODY_SPLIT]] ], [ 4, [[INNERMOST_PREHEADER]] ]
-; CHECK-NEXT: br label [[MIDDLE_HEADER_PREHEADER]]
-; CHECK: innermost.body.split1:
+; CHECK-NEXT: br label %[[MIDDLE_HEADER:.*]]
+; CHECK: [[MIDDLE_HEADER]]:
+; CHECK-NEXT: [[INDVAR_MIDDLE:%.*]] = phi i64 [ 4, %[[OUTERMOST_HEADER]] ], [ [[INDVAR_MIDDLE_NEXT:%.*]], %[[MIDDLE_LATCH:.*]] ]
+; CHECK-NEXT: br i1 [[TOBOOL71_I]], label %[[INNERMOST_PREHEADER:.*]], label %[[MIDDLE_LATCH]]
+; CHECK: [[INNERMOST_PREHEADER]]:
+; CHECK-NEXT: br label %[[INNERMOST_BODY:.*]]
+; CHECK: [[INNERMOST_BODY]]:
+; CHECK-NEXT: [[INDVAR_INNERMOST:%.*]] = phi i64 [ [[TMP1:%.*]], %[[INNERMOST_BODY]] ], [ 4, %[[INNERMOST_PREHEADER]] ]
; CHECK-NEXT: [[ARRAYIDX9_I:%.*]] = getelementptr inbounds [1 x [6 x i32]], ptr @d, i64 0, i64 [[INDVAR_INNERMOST]], i64 [[INDVAR_MIDDLE]]
; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX9_I]], align 4
-; CHECK-NEXT: [[INDVAR_INNERMOST_NEXT:%.*]] = add nsw i64 [[INDVAR_INNERMOST]], -1
-; CHECK-NEXT: [[TOBOOL5_I:%.*]] = icmp eq i64 [[INDVAR_INNERMOST_NEXT]], 0
-; CHECK-NEXT: br label [[MIDDLE_LATCH_LOOPEXIT:%.*]]
-; CHECK: innermost.body.split:
; CHECK-NEXT: [[TMP1]] = add nsw i64 [[INDVAR_INNERMOST]], -1
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
-; CHECK-NEXT: br i1 [[TMP2]], label [[OUTERMOST_LATCH]], label [[INNERMOST_BODY]]
-; CHECK: innermost.loopexit:
-; CHECK-NEXT: br label [[MIDDLE_LATCH]]
-; CHECK: middle.latch:
+; CHECK-NEXT: br i1 [[TMP2]], label %[[INNERMOST_LOOPEXIT:.*]], label %[[INNERMOST_BODY]]
+; CHECK: [[INNERMOST_LOOPEXIT]]:
+; CHECK-NEXT: br label %[[MIDDLE_LATCH]]
+; CHECK: [[MIDDLE_LATCH]]:
; CHECK-NEXT: [[INDVAR_MIDDLE_NEXT]] = add nsw i64 [[INDVAR_MIDDLE]], -1
; CHECK-NEXT: [[TOBOOL2_I:%.*]] = icmp eq i64 [[INDVAR_MIDDLE_NEXT]], 0
-; CHECK-NEXT: br i1 [[TOBOOL2_I]], label [[INNERMOST_BODY_SPLIT]], label [[MIDDLE_HEADER]]
-; CHECK: outermost.latch:
+; CHECK-NEXT: br i1 [[TOBOOL2_I]], label %[[OUTERMOST_LATCH]], label %[[MIDDLE_HEADER]]
+; CHECK: [[OUTERMOST_LATCH]]:
; CHECK-NEXT: [[INDVAR_OUTERMOST_NEXT]] = add nsw i32 [[INDVAR_OUTERMOST]], -5
; CHECK-NEXT: [[TOBOOL_I:%.*]] = icmp eq i32 [[INDVAR_OUTERMOST_NEXT]], 0
-; CHECK-NEXT: br i1 [[TOBOOL_I]], label [[OUTERMOST_EXIT:%.*]], label [[OUTERMOST_HEADER]]
-; CHECK: outermost.exit:
+; CHECK-NEXT: br i1 [[TOBOOL_I]], label %[[OUTERMOST_EXIT:.*]], label %[[OUTERMOST_HEADER]]
+; CHECK: [[OUTERMOST_EXIT]]:
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll b/llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
index cc787fa55600a6..d2a1adfc58dd45 100644
--- a/llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
+++ b/llvm/test/Transforms/LoopInterchange/pr43176-move-to-new-latch.ll
@@ -14,10 +14,10 @@
; CHECK: --- !Missed
; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: InterchangeNotProfitable
+; CHECK-NEXT: Name: Dependence
; CHECK-NEXT: Function: test1
; CHECK-NEXT: Args:
-; CHECK-NEXT: - String: Interchanging loops is not considered to improve cache locality nor vectorization.
+; CHECK-NEXT: - String: Cannot interchange loops due to dependences.
define void @test1() {
entry:
@@ -54,10 +54,10 @@ for.cond.for.end5_crit_edge: ; preds = %for.inc3
; CHECK: --- !Missed
; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: InterchangeNotProfitable
+; CHECK-NEXT: Name: Dependence
; CHECK-NEXT: Function: test2
; CHECK-NEXT: Args:
-; CHECK-NEXT: - String: Interchanging loops is not considered to improve cache locality nor vectorization.
+; CHECK-NEXT: - String: Cannot interchange loops due to dependences.
define void @test2() {
entry:
diff --git a/llvm/test/Transforms/LoopInterchange/pr43797-lcssa-for-multiple-outer-loop-blocks.ll b/llvm/test/Transforms/LoopInterchange/pr43797-lcssa-for-multiple-outer-loop-blocks.ll
index 1fe34b3d04620b..b1af701a0b868e 100644
--- a/llvm/test/Transforms/LoopInterchange/pr43797-lcssa-for-multiple-outer-loop-blocks.ll
+++ b/llvm/test/Transforms/LoopInterchange/pr43797-lcssa-for-multiple-outer-loop-blocks.ll
@@ -8,39 +8,28 @@
define void @test1() {
; CHECK-LABEL: @test1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br label [[INNER_HEADER_PREHEADER:%.*]]
-; CHECK: outer.header.preheader:
; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
; CHECK: outer.header:
-; CHECK-NEXT: [[OUTER_IDX:%.*]] = phi i64 [ [[OUTER_IDX_INC:%.*]], [[OUTER_LATCH:%.*]] ], [ 0, [[OUTER_HEADER_PREHEADER:%.*]] ]
+; CHECK-NEXT: [[OUTER_IDX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IDX_INC:%.*]], [[OUTER_LATCH:%.*]] ]
; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x [5 x double]], ptr @wdtdr, i64 0, i64 0, i64 [[OUTER_IDX]]
-; CHECK-NEXT: br label [[INNER_HEADER_SPLIT:%.*]]
-; CHECK: inner.header.preheader:
; CHECK-NEXT: br label [[INNER_HEADER:%.*]]
; CHECK: inner.header:
-; CHECK-NEXT: [[INNER_IDX:%.*]] = phi i64 [ [[TMP3:%.*]], [[INNER_LATCH_SPLIT:%.*]] ], [ 0, [[INNER_HEADER_PREHEADER]] ]
-; CHECK-NEXT: br label [[OUTER_HEADER_PREHEADER]]
-; CHECK: inner.header.split:
+; CHECK-NEXT: [[INNER_IDX:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[TMP3:%.*]], [[INNER_LATCH:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[ARRAYIDX8]], align 8
; CHECK-NEXT: store double undef, ptr [[ARRAYIDX8]], align 8
-; CHECK-NEXT: br label [[INNER_LATCH:%.*]]
+; CHECK-NEXT: br label [[INNER_LATCH]]
; CHECK: inner.latch:
-; CHECK-NEXT: [[INNER_IDX_INC:%.*]] = add nsw i64 [[INNER_IDX]], 1
-; CHECK-NEXT: br label [[INNER_EXIT:%.*]]
-; CHECK: inner.latch.split:
-; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ [[OUTER_V:%.*]], [[OUTER_LATCH]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = phi i64 [ [[OUTER_IDX_INC]], [[OUTER_LATCH]] ]
; CHECK-NEXT: [[TMP3]] = add nsw i64 [[INNER_IDX]], 1
; CHECK-NEXT: br i1 false, label [[INNER_HEADER]], label [[OUTER_EXIT:%.*]]
; CHECK: inner.exit:
-; CHECK-NEXT: [[OUTER_V]] = add nsw i64 [[OUTER_IDX]], 1
+; CHECK-NEXT: [[OUTER_V:%.*]] = add nsw i64 [[OUTER_IDX]], 1
; CHECK-NEXT: br label [[OUTER_LATCH]]
; CHECK: outer.latch:
; CHECK-NEXT: [[OUTER_IDX_INC]] = add nsw i64 [[OUTER_IDX]], 1
-; CHECK-NEXT: br i1 false, label [[OUTER_HEADER]], label [[INNER_LATCH_SPLIT]]
+; CHECK-NEXT: br i1 false, label [[OUTER_HEADER]], label [[INNER_LATCH_SPLIT:%.*]]
; CHECK: outer.exit:
-; CHECK-NEXT: [[EXIT1_LCSSA:%.*]] = phi i64 [ [[TMP1]], [[INNER_LATCH_SPLIT]] ]
-; CHECK-NEXT: [[EXIT2_LCSSA:%.*]] = phi i64 [ [[TMP2]], [[INNER_LATCH_SPLIT]] ]
+; CHECK-NEXT: [[EXIT1_LCSSA:%.*]] = phi i64 [ [[OUTER_V]], [[OUTER_LATCH]] ]
+; CHECK-NEXT: [[EXIT2_LCSSA:%.*]] = phi i64 [ [[OUTER_IDX_INC]], [[OUTER_LATCH]] ]
; CHECK-NEXT: ret void
;
entry:
@@ -82,39 +71,30 @@ define void @test2(i1 %cond) {
; CHECK: outer.header.preheader:
; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
; CHECK: outer.header:
-; CHECK-NEXT: [[OUTER_IDX:%.*]] = phi i64 [ [[OUTER_IDX_INC:%.*]], [[OUTER_LATCH:%.*]] ], [ 0, [[OUTER_HEADER_PREHEADER:%.*]] ]
+; CHECK-NEXT: [[OUTER_IDX:%.*]] = phi i64 [ [[OUTER_IDX_INC:%.*]], [[OUTER_LATCH:%.*]] ], [ 0, [[INNER_HEADER_PREHEADER]] ]
; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x [5 x double]], ptr @wdtdr, i64 0, i64 0, i64 [[OUTER_IDX]]
-; CHECK-NEXT: br label [[INNER_HEADER_SPLIT:%.*]]
-; CHECK: inner.header.preheader:
; CHECK-NEXT: br label [[INNER_HEADER:%.*]]
; CHECK: inner.header:
-; CHECK-NEXT: [[INNER_IDX:%.*]] = phi i64 [ [[TMP3:%.*]], [[INNER_LATCH_SPLIT:%.*]] ], [ 0, [[INNER_HEADER_PREHEADER]] ]
-; CHECK-NEXT: br label [[OUTER_HEADER_PREHEADER]]
-; CHECK: inner.header.split:
+; CHECK-NEXT: [[INNER_IDX:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[TMP3:%.*]], [[INNER_LATCH:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[ARRAYIDX8]], align 8
; CHECK-NEXT: store double undef, ptr [[ARRAYIDX8]], align 8
-; CHECK-NEXT: br label [[INNER_LATCH:%.*]]
+; CHECK-NEXT: br label [[INNER_LATCH]]
; CHECK: inner.latch:
-; CHECK-NEXT: [[INNER_IDX_INC:%.*]] = add nsw i64 [[INNER_IDX]], 1
-; CHECK-NEXT: br label [[INNER_EXIT:%.*]]
-; CHECK: inner.latch.split:
-; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ [[OUTER_IDX_INC]], [[OUTER_LATCH]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = phi i64 [ [[OUTER_V:%.*]], [[OUTER_LATCH]] ]
; CHECK-NEXT: [[TMP3]] = add nsw i64 [[INNER_IDX]], 1
; CHECK-NEXT: br i1 false, label [[INNER_HEADER]], label [[OUTER_EXIT_LOOPEXIT:%.*]]
; CHECK: inner.exit:
-; CHECK-NEXT: [[OUTER_V]] = add nsw i64 [[OUTER_IDX]], 1
+; CHECK-NEXT: [[OUTER_V:%.*]] = add nsw i64 [[OUTER_IDX]], 1
; CHECK-NEXT: br label [[OUTER_LATCH]]
; CHECK: outer.latch:
; CHECK-NEXT: [[OUTER_IDX_INC]] = add nsw i64 [[OUTER_IDX]], 1
-; CHECK-NEXT: br i1 false, label [[OUTER_HEADER]], label [[INNER_LATCH_SPLIT]]
+; CHECK-NEXT: br i1 false, label [[OUTER_HEADER]], label [[INNER_LATCH_SPLIT:%.*]]
; CHECK: outer.exit.loopexit:
-; CHECK-NEXT: [[OUTER_IDX_INC_LCSSA:%.*]] = phi i64 [ [[TMP1]], [[INNER_LATCH_SPLIT]] ]
-; CHECK-NEXT: [[OUTER_V_LCSSA:%.*]] = phi i64 [ [[TMP2]], [[INNER_LATCH_SPLIT]] ]
+; CHECK-NEXT: [[OUTER_IDX_INC_LCSSA:%.*]] = phi i64 [ [[OUTER_IDX_INC]], [[OUTER_LATCH]] ]
+; CHECK-NEXT: [[OUTER_V_LCSSA:%.*]] = phi i64 [ [[OUTER_V]], [[OUTER_LATCH]] ]
; CHECK-NEXT: br label [[OUTER_EXIT]]
; CHECK: outer.exit:
-; CHECK-NEXT: [[EXIT1_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_V_LCSSA]], [[OUTER_EXIT_LOOPEXIT]] ]
-; CHECK-NEXT: [[EXIT2_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[OUTER_IDX_INC_LCSSA]], [[OUTER_EXIT_LOOPEXIT]] ]
+; CHECK-NEXT: [[EXIT1_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_V_LCSSA]], [[INNER_LATCH_SPLIT]] ]
+; CHECK-NEXT: [[EXIT2_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[OUTER_IDX_INC_LCSSA]], [[INNER_LATCH_SPLIT]] ]
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/LoopInterchange/profitability.ll b/llvm/test/Transforms/LoopInterchange/profitability.ll
index 505c6c422beb6d..ddd90a35846282 100644
--- a/llvm/test/Transforms/LoopInterchange/profitability.ll
+++ b/llvm/test/Transforms/LoopInterchange/profitability.ll
@@ -1,5 +1,5 @@
; RUN: opt < %s -passes=loop-interchange -cache-line-size=64 -pass-remarks-output=%t -verify-dom-info -verify-loop-info \
-; RUN: -pass-remarks=loop-interchange -pass-remarks-missed=loop-interchange
+; RUN: -pass-remarks=loop-interchange -pass-remarks-missed=loop-interchange -S
; RUN: FileCheck -input-file %t %s
; RUN: opt < %s -passes=loop-interchange,loop-interchange -cache-line-size=64 \
@@ -174,23 +174,15 @@ for.end12:
;; for(int i=1;i<100;i++)
;; for(int j=1;j<100;j++)
;; A[j][0] = A[j][0] + B[j][i];
+;
+; FIXME
-; CHECK: Name: Interchanged
+; CHECK: Name: Dependence
; CHECK-NEXT: Function: interchange_05
-; PROFIT-LABEL: --- !Passed
-; PROFIT-NEXT: Pass: loop-interchange
-; PROFIT-NEXT: Name: Interchanged
-; PROFIT-LABEL: Function: interchange_05
-; PROFIT-NEXT: Args:
-; PROFIT-NEXT: - String: Loop interchanged with enclosing loop.
-; PROFIT-NEXT: ...
-; PROFIT: --- !Missed
-; PROFIT-NEXT: Pass: loop-interchange
-; PROFIT-NEXT: Name: InterchangeNotProfitable
-; PROFIT-NEXT: Function: interchange_05
+; PROFIT: Function: interchange_05
; PROFIT-NEXT: Args:
-; PROFIT-NEXT: - String: Interchanging loops is not considered to improve cache locality nor vectorization.
+; PROFIT-NEXT: - String: Cannot interchange loops due to dependences
; PROFIT-NEXT: ...
define void @interchange_05() {
entry:
diff --git a/llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll b/llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
index fa2021a15a0801..eea0c2635d5959 100644
--- a/llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
+++ b/llvm/test/Transforms/LoopInterchange/reductions-across-inner-and-outer-loop.ll
@@ -153,7 +153,7 @@ for1.loopexit: ; preds = %for1.inc
; Check that we do not interchange if reduction is stored in an invariant address inside inner loop
; REMARKS: --- !Missed
; REMARKS-NEXT: Pass: loop-interchange
-; REMARKS-NEXT: Name: UnsupportedPHIOuter
+; REMARKS-NEXT: Name: Dependence
; REMARKS-NEXT: Function: test4
define i64 @test4(ptr %Arr, ptr %dst) {
diff --git a/llvm/test/Transforms/LoopInterchange/vector-gep-operand.ll b/llvm/test/Transforms/LoopInterchange/vector-gep-operand.ll
index 03e3b4b7408b5c..b180f2414fb140 100644
--- a/llvm/test/Transforms/LoopInterchange/vector-gep-operand.ll
+++ b/llvm/test/Transforms/LoopInterchange/vector-gep-operand.ll
@@ -6,35 +6,25 @@
define void @test(ptr noalias %src, ptr %dst) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br label [[INNER_PREHEADER:%.*]]
-; CHECK: outer.header.preheader:
; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
; CHECK: outer.header:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_NEXT:%.*]], [[OUTER_LATCH:%.*]] ], [ 0, [[OUTER_HEADER_PREHEADER:%.*]] ]
-; CHECK-NEXT: br label [[INNER_SPLIT1:%.*]]
-; CHECK: inner.preheader:
; CHECK-NEXT: br label [[INNER:%.*]]
; CHECK: inner:
-; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[TMP0:%.*]], [[INNER_SPLIT:%.*]] ], [ 0, [[INNER_PREHEADER]] ]
-; CHECK-NEXT: br label [[OUTER_HEADER_PREHEADER]]
-; CHECK: inner.split1:
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[TMP0:%.*]], [[INNER]] ]
; CHECK-NEXT: [[SRC_GEP:%.*]] = getelementptr inbounds [256 x float], ptr [[SRC:%.*]], <2 x i64> <i64 0, i64 1>, i64 [[J]]
; CHECK-NEXT: [[SRC_0:%.*]] = extractelement <2 x ptr> [[SRC_GEP]], i32 0
; CHECK-NEXT: [[LV_0:%.*]] = load float, ptr [[SRC_0]], align 4
; CHECK-NEXT: [[ADD_0:%.*]] = fadd float [[LV_0]], 1.000000e+00
; CHECK-NEXT: [[DST_GEP:%.*]] = getelementptr inbounds float, ptr [[DST:%.*]], i64 [[J]]
; CHECK-NEXT: store float [[ADD_0]], ptr [[DST_GEP]], align 4
-; CHECK-NEXT: [[J_NEXT:%.*]] = add nuw nsw i64 [[J]], 1
-; CHECK-NEXT: [[INNER_EXITCOND:%.*]] = icmp eq i64 [[J_NEXT]], 100
-; CHECK-NEXT: br label [[OUTER_LATCH]]
-; CHECK: inner.split:
; CHECK-NEXT: [[TMP0]] = add nuw nsw i64 [[J]], 1
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 100
-; CHECK-NEXT: br i1 [[TMP1]], label [[EXIT:%.*]], label [[INNER]]
+; CHECK-NEXT: br i1 [[TMP1]], label [[OUTER_LATCH]], label [[INNER]]
; CHECK: outer.latch:
; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i32 [[I]], 1
; CHECK-NEXT: [[OUTER_EXITCOND:%.*]] = icmp eq i32 [[I_NEXT]], 100
-; CHECK-NEXT: br i1 [[OUTER_EXITCOND]], label [[INNER_SPLIT]], label [[OUTER_HEADER]]
+; CHECK-NEXT: br i1 [[OUTER_EXITCOND]], label [[INNER_SPLIT:%.*]], label [[OUTER_HEADER]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
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