[llvm] [RISCV] Add missing check before accessing pointer (PR #121816)
Mikhail R. Gadelha via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 7 07:59:29 PST 2025
https://github.com/mikhailramalho updated https://github.com/llvm/llvm-project/pull/121816
>From 20a1b186fbef0b852fa0c3ac16f96cccbccff0d8 Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Mon, 6 Jan 2025 18:35:47 -0300
Subject: [PATCH 1/8] Added test case
---
.../CodeGen/RISCV/mul_sext_shl_constant.ll | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll
diff --git a/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll
new file mode 100644
index 00000000000000..8f0b53e1144bde
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefixes=NO-ZBA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zba < %s | FileCheck -check-prefixes=ZBA %s
+
+define ptr @g(ptr %0, i32 %1) {
+; NO-ZBA-LABEL: g:
+; NO-ZBA: # %bb.0:
+; NO-ZBA-NEXT: slli a2, a1, 1
+; NO-ZBA-NEXT: add a2, a2, a1
+; NO-ZBA-NEXT: sllw a1, a2, a1
+; NO-ZBA-NEXT: li a0, 0
+; NO-ZBA-NEXT: ret
+;
+; ZBA-LABEL: g:
+; ZBA: # %bb.0:
+; ZBA-NEXT: sh1add a2, a1, a1
+; ZBA-NEXT: sllw a1, a2, a1
+; ZBA-NEXT: li a0, 0
+; ZBA-NEXT: ret
+ %3 = mul i32 %1, 3
+ %4 = shl i32 %3, %1
+ %5 = sext i32 %4 to i64
+ %6 = inttoptr i64 %5 to ptr
+ %7 = icmp ugt ptr %0, %6
+ br i1 %7, label %10, label %8
+
+8: ; preds = %2
+ %9 = load i8, ptr null, align 1
+ br label %10
+
+10: ; preds = %8, %2
+ ret ptr null
+}
>From 14d9bb21c41d79876fde0b9ca98095f827cfaa3a Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Tue, 7 Jan 2025 11:54:34 -0300
Subject: [PATCH 2/8] Added slightly different test case
---
.../CodeGen/RISCV/add_sext_shl_constant.ll | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
index fe89b4aa24171c..87de8965a20360 100644
--- a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
+++ b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
@@ -320,6 +320,28 @@ define i64 @add_shl_moreOneUse_sh3add(i64 %x) {
ret i64 %add
}
+define ptr @add_shl_sext_inttoptr(ptr %0, i32 %1) {
+; RV64-LABEL: add_shl_sext_inttoptr:
+; RV64: # %bb.0:
+; RV64-NEXT: addi a2, a1, 3
+; RV64-NEXT: sllw a1, a2, a1
+; RV64-NEXT: li a0, 0
+; RV64-NEXT: ret
+ %3 = add i32 %1, 3
+ %4 = shl i32 %3, %1
+ %5 = sext i32 %4 to i64
+ %6 = inttoptr i64 %5 to ptr
+ %7 = icmp ugt ptr %0, %6
+ br i1 %7, label %10, label %8
+
+8:
+ %9 = load i8, ptr null, align 1
+ br label %10
+
+10:
+ ret ptr null
+}
+
define i64 @add_shl_moreOneUse_sh4add(i64 %x) {
; RV64-LABEL: add_shl_moreOneUse_sh4add:
; RV64: # %bb.0:
>From 10ba6e65aa9da43bf6393c3b7662e18cc300209f Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Tue, 7 Jan 2025 11:55:05 -0300
Subject: [PATCH 3/8] Removed old test
---
.../CodeGen/RISCV/mul_sext_shl_constant.ll | 33 -------------------
1 file changed, 33 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll
diff --git a/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll
deleted file mode 100644
index 8f0b53e1144bde..00000000000000
--- a/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll
+++ /dev/null
@@ -1,33 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefixes=NO-ZBA %s
-; RUN: llc -mtriple=riscv64 -mattr=+zba < %s | FileCheck -check-prefixes=ZBA %s
-
-define ptr @g(ptr %0, i32 %1) {
-; NO-ZBA-LABEL: g:
-; NO-ZBA: # %bb.0:
-; NO-ZBA-NEXT: slli a2, a1, 1
-; NO-ZBA-NEXT: add a2, a2, a1
-; NO-ZBA-NEXT: sllw a1, a2, a1
-; NO-ZBA-NEXT: li a0, 0
-; NO-ZBA-NEXT: ret
-;
-; ZBA-LABEL: g:
-; ZBA: # %bb.0:
-; ZBA-NEXT: sh1add a2, a1, a1
-; ZBA-NEXT: sllw a1, a2, a1
-; ZBA-NEXT: li a0, 0
-; ZBA-NEXT: ret
- %3 = mul i32 %1, 3
- %4 = shl i32 %3, %1
- %5 = sext i32 %4 to i64
- %6 = inttoptr i64 %5 to ptr
- %7 = icmp ugt ptr %0, %6
- br i1 %7, label %10, label %8
-
-8: ; preds = %2
- %9 = load i8, ptr null, align 1
- br label %10
-
-10: ; preds = %8, %2
- ret ptr null
-}
>From 87317cd34ccc355f721dc6b8757f5724acaebb2f Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Tue, 7 Jan 2025 12:24:21 -0300
Subject: [PATCH 4/8] Reduce test case
Signed-off-by: Mikhail R. Gadelha <mikhail at igalia.com>
---
.../CodeGen/RISCV/add_sext_shl_constant.ll | 20 +++++--------------
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
index 87de8965a20360..303363612ff019 100644
--- a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
+++ b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
@@ -320,26 +320,16 @@ define i64 @add_shl_moreOneUse_sh3add(i64 %x) {
ret i64 %add
}
-define ptr @add_shl_sext_inttoptr(ptr %0, i32 %1) {
-; RV64-LABEL: add_shl_sext_inttoptr:
+define i64 @add_shl_sext(ptr %0, i32 %1) {
+; RV64-LABEL: add_shl_sext:
; RV64: # %bb.0:
-; RV64-NEXT: addi a2, a1, 3
-; RV64-NEXT: sllw a1, a2, a1
-; RV64-NEXT: li a0, 0
+; RV64-NEXT: addi a0, a1, 3
+; RV64-NEXT: sllw a0, a0, a1
; RV64-NEXT: ret
%3 = add i32 %1, 3
%4 = shl i32 %3, %1
%5 = sext i32 %4 to i64
- %6 = inttoptr i64 %5 to ptr
- %7 = icmp ugt ptr %0, %6
- br i1 %7, label %10, label %8
-
-8:
- %9 = load i8, ptr null, align 1
- br label %10
-
-10:
- ret ptr null
+ ret i64 %5
}
define i64 @add_shl_moreOneUse_sh4add(i64 %x) {
>From d04d4080869dc6d940c0595ffc6bc4b99fe6e9b7 Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail.ramalho at gmail.com>
Date: Tue, 7 Jan 2025 12:37:07 -0300
Subject: [PATCH 5/8] Update llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
Co-authored-by: Luke Lau <luke_lau at icloud.com>
---
llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
index 303363612ff019..fc976b5459d285 100644
--- a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
+++ b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
@@ -320,7 +320,7 @@ define i64 @add_shl_moreOneUse_sh3add(i64 %x) {
ret i64 %add
}
-define i64 @add_shl_sext(ptr %0, i32 %1) {
+define i64 @add_shl_sext(i32 %1) {
; RV64-LABEL: add_shl_sext:
; RV64: # %bb.0:
; RV64-NEXT: addi a0, a1, 3
>From 0c1a2b88a89ae3b510e3b00ec18690b337e2e842 Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail.ramalho at gmail.com>
Date: Tue, 7 Jan 2025 12:37:34 -0300
Subject: [PATCH 6/8] Update llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
Co-authored-by: Luke Lau <luke_lau at icloud.com>
>From 75e8285a6e5c36eccf9e67b18df63a962668385a Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail.ramalho at gmail.com>
Date: Tue, 7 Jan 2025 12:38:09 -0300
Subject: [PATCH 7/8] Update llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
Co-authored-by: Luke Lau <luke_lau at icloud.com>
>From 9b5b3aa1e282098d20ad23a26854dd2c75826ef4 Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Tue, 7 Jan 2025 12:39:58 -0300
Subject: [PATCH 8/8] Updated generated asm
---
llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
index fc976b5459d285..7bd10ae71cf995 100644
--- a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
+++ b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
@@ -323,8 +323,8 @@ define i64 @add_shl_moreOneUse_sh3add(i64 %x) {
define i64 @add_shl_sext(i32 %1) {
; RV64-LABEL: add_shl_sext:
; RV64: # %bb.0:
-; RV64-NEXT: addi a0, a1, 3
-; RV64-NEXT: sllw a0, a0, a1
+; RV64-NEXT: addi a1, a0, 3
+; RV64-NEXT: sllw a0, a1, a0
; RV64-NEXT: ret
%3 = add i32 %1, 3
%4 = shl i32 %3, %1
More information about the llvm-commits
mailing list