[llvm] [RISCV] Add missing check before accessing pointer (PR #121816)

[Mikhail R. Gadelha via llvm-commits]

https://github.com/mikhailramalho updated https://github.com/llvm/llvm-project/pull/121816

>From 20a1b186fbef0b852fa0c3ac16f96cccbccff0d8 Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Mon, 6 Jan 2025 18:35:47 -0300
Subject: [PATCH 1/3] Added test case

---
 .../CodeGen/RISCV/mul_sext_shl_constant.ll    | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll

diff --git a/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll
new file mode 100644
index 00000000000000..8f0b53e1144bde
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefixes=NO-ZBA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zba < %s | FileCheck -check-prefixes=ZBA %s
+
+define ptr @g(ptr %0, i32 %1) {
+; NO-ZBA-LABEL: g:
+; NO-ZBA:       # %bb.0:
+; NO-ZBA-NEXT:    slli a2, a1, 1
+; NO-ZBA-NEXT:    add a2, a2, a1
+; NO-ZBA-NEXT:    sllw a1, a2, a1
+; NO-ZBA-NEXT:    li a0, 0
+; NO-ZBA-NEXT:    ret
+;
+; ZBA-LABEL: g:
+; ZBA:       # %bb.0:
+; ZBA-NEXT:    sh1add a2, a1, a1
+; ZBA-NEXT:    sllw a1, a2, a1
+; ZBA-NEXT:    li a0, 0
+; ZBA-NEXT:    ret
+  %3 = mul i32 %1, 3
+  %4 = shl i32 %3, %1
+  %5 = sext i32 %4 to i64
+  %6 = inttoptr i64 %5 to ptr
+  %7 = icmp ugt ptr %0, %6
+  br i1 %7, label %10, label %8
+
+8:                                                ; preds = %2
+  %9 = load i8, ptr null, align 1
+  br label %10
+
+10:                                               ; preds = %8, %2
+  ret ptr null
+}

>From 14d9bb21c41d79876fde0b9ca98095f827cfaa3a Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Tue, 7 Jan 2025 11:54:34 -0300
Subject: [PATCH 2/3] Added slightly different test case

---
 .../CodeGen/RISCV/add_sext_shl_constant.ll    | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
index fe89b4aa24171c..87de8965a20360 100644
--- a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
+++ b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
@@ -320,6 +320,28 @@ define i64 @add_shl_moreOneUse_sh3add(i64 %x) {
   ret i64 %add
 }
 
+define ptr @add_shl_sext_inttoptr(ptr %0, i32 %1) {
+; RV64-LABEL: add_shl_sext_inttoptr:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a2, a1, 3
+; RV64-NEXT:    sllw a1, a2, a1
+; RV64-NEXT:    li a0, 0
+; RV64-NEXT:    ret
+  %3 = add i32 %1, 3
+  %4 = shl i32 %3, %1
+  %5 = sext i32 %4 to i64
+  %6 = inttoptr i64 %5 to ptr
+  %7 = icmp ugt ptr %0, %6
+  br i1 %7, label %10, label %8
+
+8:
+  %9 = load i8, ptr null, align 1
+  br label %10
+
+10:
+  ret ptr null
+}
+
 define i64 @add_shl_moreOneUse_sh4add(i64 %x) {
 ; RV64-LABEL: add_shl_moreOneUse_sh4add:
 ; RV64:       # %bb.0:

>From 10ba6e65aa9da43bf6393c3b7662e18cc300209f Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Tue, 7 Jan 2025 11:55:05 -0300
Subject: [PATCH 3/3] Removed old test

---
 .../CodeGen/RISCV/mul_sext_shl_constant.ll    | 33 -------------------
 1 file changed, 33 deletions(-)
 delete mode 100644 llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll

diff --git a/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll
deleted file mode 100644
index 8f0b53e1144bde..00000000000000
--- a/llvm/test/CodeGen/RISCV/mul_sext_shl_constant.ll
+++ /dev/null
@@ -1,33 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefixes=NO-ZBA %s
-; RUN: llc -mtriple=riscv64 -mattr=+zba < %s | FileCheck -check-prefixes=ZBA %s
-
-define ptr @g(ptr %0, i32 %1) {
-; NO-ZBA-LABEL: g:
-; NO-ZBA:       # %bb.0:
-; NO-ZBA-NEXT:    slli a2, a1, 1
-; NO-ZBA-NEXT:    add a2, a2, a1
-; NO-ZBA-NEXT:    sllw a1, a2, a1
-; NO-ZBA-NEXT:    li a0, 0
-; NO-ZBA-NEXT:    ret
-;
-; ZBA-LABEL: g:
-; ZBA:       # %bb.0:
-; ZBA-NEXT:    sh1add a2, a1, a1
-; ZBA-NEXT:    sllw a1, a2, a1
-; ZBA-NEXT:    li a0, 0
-; ZBA-NEXT:    ret
-  %3 = mul i32 %1, 3
-  %4 = shl i32 %3, %1
-  %5 = sext i32 %4 to i64
-  %6 = inttoptr i64 %5 to ptr
-  %7 = icmp ugt ptr %0, %6
-  br i1 %7, label %10, label %8
-
-8:                                                ; preds = %2
-  %9 = load i8, ptr null, align 1
-  br label %10
-
-10:                                               ; preds = %8, %2
-  ret ptr null
-}