[llvm] [ADT] Make null PointerUnion with different active members compare equal (PR #121847)

[Sergei Barannikov via llvm-commits]

================
@@ -134,10 +134,10 @@ const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister(
 
   // If the register already has a class, fallback to MRI::constrainRegClass.
   auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
-  if (isa<const TargetRegisterClass *>(RegClassOrBank))
+  if (isa_and_present<const TargetRegisterClass *>(RegClassOrBank))
----------------
s-barannikov wrote:

Input gMIR to instruction selector shouldn't contain registers without class/bank.
Such registers are created during instruction selection if an imported SelectionDAG pattern contains several instructions in the "destination DAG" of the pattern:

```
def : GCNPat <
  (UniformUnaryFrag<fabs> (v2f16 SReg_32:$src)),
  (S_AND_B32 SReg_32:$src, (S_MOV_B32 (i32 0x7fff7fff)))
>;
```

This is what `-gen-global-isel` generates for this pattern:
```
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        ...
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
        ...
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_RootConstrainSelectedInstOperands,
```

`GIR_MakeTempReg` creates a register without class/bank for the result of the `S_MOV_B32`. The register gets its class when executing `GIR_ConstrainSelectedInstOperands` action, which calls this function, which calls `MRI.setRegClass()` at the end.

I don't know if this should be considered a bug. If it should, I can try to address it separately (probably in #121270).

---
(Unrelated to this PR). Note that the type of the temporary register is `s1`. It is chosen [arbitrarily](https://github.com/llvm/llvm-project/blob/0575815b70b486240ace728a33f756cea8fe58fa/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp#L4279).


https://github.com/llvm/llvm-project/pull/121847