[llvm] [NVPTX][SelectionDAG] Add IMAD combine rules + infra to disable default SelectionDAG rules for testing (PR #121724)

via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 6 22:04:41 PST 2025


github-actions[bot] wrote:

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git-clang-format --diff 9abcca5e25296aea49288ad63901f9e0a332dad4 508628e58285ef94d2119e1007782fcd776f46ca --extensions h,cpp -- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 362dc4338c..4670f9206b 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -4458,7 +4458,8 @@ PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
       return SDValue();
 
     SDLoc DL(N);
-    SDValue Mul = DCI.DAG.getNode(ISD::MUL, DL, VT, M->getOperand(0), M->getOperand(1));
+    SDValue Mul =
+        DCI.DAG.getNode(ISD::MUL, DL, VT, M->getOperand(0), M->getOperand(1));
     SDValue MAD = DCI.DAG.getNode(ISD::ADD, DL, VT, Mul, N1);
     return DCI.DAG.getSelect(SDLoc(N), VT, N0->getOperand(0),
                              ((ZeroOpNum == 1) ? N1 : MAD),

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https://github.com/llvm/llvm-project/pull/121724


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