[llvm] [RISCV] Fix the cost of `llvm.vector.reduce.and` (PR #119160)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 6 20:24:25 PST 2025


================
@@ -0,0 +1,548 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-VL128B
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-VL128B
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-VL256B
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvl256b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-VL256B
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-VL512B
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-VL512B
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvl1024b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-VL1024B
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvl1024b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-VL1024B
+
+define zeroext i1 @vreduce_and_v1i1(<1 x i1> %v) {
+; CHECK-LABEL: vreduce_and_v1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_v2i1(<2 x i1> %v) {
+; CHECK-LABEL: vreduce_and_v2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_v4i1(<4 x i1> %v) {
+; CHECK-VL128B-LABEL: vreduce_and_v4i1:
+; CHECK-VL128B:       # %bb.0:
+; CHECK-VL128B-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-VL128B-NEXT:    vmnot.m v8, v0
+; CHECK-VL128B-NEXT:    vcpop.m a0, v8
+; CHECK-VL128B-NEXT:    seqz a0, a0
+; CHECK-VL128B-NEXT:    ret
+;
+; CHECK-VL256B-LABEL: vreduce_and_v4i1:
+; CHECK-VL256B:       # %bb.0:
+; CHECK-VL256B-NEXT:    vsetivli zero, 4, e8, mf8, ta, ma
+; CHECK-VL256B-NEXT:    vmnot.m v8, v0
+; CHECK-VL256B-NEXT:    vcpop.m a0, v8
+; CHECK-VL256B-NEXT:    seqz a0, a0
+; CHECK-VL256B-NEXT:    ret
+;
+; CHECK-VL512B-LABEL: vreduce_and_v4i1:
+; CHECK-VL512B:       # %bb.0:
+; CHECK-VL512B-NEXT:    vsetivli zero, 4, e8, mf8, ta, ma
+; CHECK-VL512B-NEXT:    vmnot.m v8, v0
+; CHECK-VL512B-NEXT:    vcpop.m a0, v8
+; CHECK-VL512B-NEXT:    seqz a0, a0
+; CHECK-VL512B-NEXT:    ret
+;
+; CHECK-VL1024B-LABEL: vreduce_and_v4i1:
+; CHECK-VL1024B:       # %bb.0:
+; CHECK-VL1024B-NEXT:    vsetivli zero, 4, e8, mf8, ta, ma
+; CHECK-VL1024B-NEXT:    vmnot.m v8, v0
+; CHECK-VL1024B-NEXT:    vcpop.m a0, v8
+; CHECK-VL1024B-NEXT:    seqz a0, a0
+; CHECK-VL1024B-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_v8i1(<8 x i1> %v) {
+; CHECK-VL128B-LABEL: vreduce_and_v8i1:
+; CHECK-VL128B:       # %bb.0:
+; CHECK-VL128B-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-VL128B-NEXT:    vmnot.m v8, v0
+; CHECK-VL128B-NEXT:    vcpop.m a0, v8
+; CHECK-VL128B-NEXT:    seqz a0, a0
+; CHECK-VL128B-NEXT:    ret
+;
+; CHECK-VL256B-LABEL: vreduce_and_v8i1:
+; CHECK-VL256B:       # %bb.0:
+; CHECK-VL256B-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
+; CHECK-VL256B-NEXT:    vmnot.m v8, v0
+; CHECK-VL256B-NEXT:    vcpop.m a0, v8
+; CHECK-VL256B-NEXT:    seqz a0, a0
+; CHECK-VL256B-NEXT:    ret
+;
+; CHECK-VL512B-LABEL: vreduce_and_v8i1:
+; CHECK-VL512B:       # %bb.0:
+; CHECK-VL512B-NEXT:    vsetivli zero, 8, e8, mf8, ta, ma
+; CHECK-VL512B-NEXT:    vmnot.m v8, v0
+; CHECK-VL512B-NEXT:    vcpop.m a0, v8
+; CHECK-VL512B-NEXT:    seqz a0, a0
+; CHECK-VL512B-NEXT:    ret
+;
+; CHECK-VL1024B-LABEL: vreduce_and_v8i1:
+; CHECK-VL1024B:       # %bb.0:
+; CHECK-VL1024B-NEXT:    vsetivli zero, 8, e8, mf8, ta, ma
+; CHECK-VL1024B-NEXT:    vmnot.m v8, v0
+; CHECK-VL1024B-NEXT:    vcpop.m a0, v8
+; CHECK-VL1024B-NEXT:    seqz a0, a0
+; CHECK-VL1024B-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_v16i1(<16 x i1> %v) {
+; CHECK-VL128B-LABEL: vreduce_and_v16i1:
+; CHECK-VL128B:       # %bb.0:
+; CHECK-VL128B-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-VL128B-NEXT:    vmnot.m v8, v0
+; CHECK-VL128B-NEXT:    vcpop.m a0, v8
+; CHECK-VL128B-NEXT:    seqz a0, a0
+; CHECK-VL128B-NEXT:    ret
+;
+; CHECK-VL256B-LABEL: vreduce_and_v16i1:
+; CHECK-VL256B:       # %bb.0:
+; CHECK-VL256B-NEXT:    vsetivli zero, 16, e8, mf2, ta, ma
+; CHECK-VL256B-NEXT:    vmnot.m v8, v0
+; CHECK-VL256B-NEXT:    vcpop.m a0, v8
+; CHECK-VL256B-NEXT:    seqz a0, a0
+; CHECK-VL256B-NEXT:    ret
+;
+; CHECK-VL512B-LABEL: vreduce_and_v16i1:
+; CHECK-VL512B:       # %bb.0:
+; CHECK-VL512B-NEXT:    vsetivli zero, 16, e8, mf4, ta, ma
+; CHECK-VL512B-NEXT:    vmnot.m v8, v0
+; CHECK-VL512B-NEXT:    vcpop.m a0, v8
+; CHECK-VL512B-NEXT:    seqz a0, a0
+; CHECK-VL512B-NEXT:    ret
+;
+; CHECK-VL1024B-LABEL: vreduce_and_v16i1:
+; CHECK-VL1024B:       # %bb.0:
+; CHECK-VL1024B-NEXT:    vsetivli zero, 16, e8, mf8, ta, ma
+; CHECK-VL1024B-NEXT:    vmnot.m v8, v0
+; CHECK-VL1024B-NEXT:    vcpop.m a0, v8
+; CHECK-VL1024B-NEXT:    seqz a0, a0
+; CHECK-VL1024B-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_v32i1(<32 x i1> %v) {
+; CHECK-VL128B-LABEL: vreduce_and_v32i1:
+; CHECK-VL128B:       # %bb.0:
+; CHECK-VL128B-NEXT:    li a0, 32
+; CHECK-VL128B-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-VL128B-NEXT:    vmnot.m v8, v0
+; CHECK-VL128B-NEXT:    vcpop.m a0, v8
+; CHECK-VL128B-NEXT:    seqz a0, a0
+; CHECK-VL128B-NEXT:    ret
+;
+; CHECK-VL256B-LABEL: vreduce_and_v32i1:
+; CHECK-VL256B:       # %bb.0:
+; CHECK-VL256B-NEXT:    li a0, 32
+; CHECK-VL256B-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-VL256B-NEXT:    vmnot.m v8, v0
+; CHECK-VL256B-NEXT:    vcpop.m a0, v8
+; CHECK-VL256B-NEXT:    seqz a0, a0
+; CHECK-VL256B-NEXT:    ret
+;
+; CHECK-VL512B-LABEL: vreduce_and_v32i1:
+; CHECK-VL512B:       # %bb.0:
+; CHECK-VL512B-NEXT:    li a0, 32
+; CHECK-VL512B-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-VL512B-NEXT:    vmnot.m v8, v0
+; CHECK-VL512B-NEXT:    vcpop.m a0, v8
+; CHECK-VL512B-NEXT:    seqz a0, a0
+; CHECK-VL512B-NEXT:    ret
+;
+; CHECK-VL1024B-LABEL: vreduce_and_v32i1:
+; CHECK-VL1024B:       # %bb.0:
+; CHECK-VL1024B-NEXT:    li a0, 32
+; CHECK-VL1024B-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-VL1024B-NEXT:    vmnot.m v8, v0
+; CHECK-VL1024B-NEXT:    vcpop.m a0, v8
+; CHECK-VL1024B-NEXT:    seqz a0, a0
+; CHECK-VL1024B-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_v64i1(<64 x i1> %v) {
+; CHECK-VL128B-LABEL: vreduce_and_v64i1:
+; CHECK-VL128B:       # %bb.0:
+; CHECK-VL128B-NEXT:    li a0, 64
+; CHECK-VL128B-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-VL128B-NEXT:    vmnot.m v8, v0
+; CHECK-VL128B-NEXT:    vcpop.m a0, v8
+; CHECK-VL128B-NEXT:    seqz a0, a0
+; CHECK-VL128B-NEXT:    ret
+;
+; CHECK-VL256B-LABEL: vreduce_and_v64i1:
+; CHECK-VL256B:       # %bb.0:
+; CHECK-VL256B-NEXT:    li a0, 64
+; CHECK-VL256B-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-VL256B-NEXT:    vmnot.m v8, v0
+; CHECK-VL256B-NEXT:    vcpop.m a0, v8
+; CHECK-VL256B-NEXT:    seqz a0, a0
+; CHECK-VL256B-NEXT:    ret
+;
+; CHECK-VL512B-LABEL: vreduce_and_v64i1:
+; CHECK-VL512B:       # %bb.0:
+; CHECK-VL512B-NEXT:    li a0, 64
+; CHECK-VL512B-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-VL512B-NEXT:    vmnot.m v8, v0
+; CHECK-VL512B-NEXT:    vcpop.m a0, v8
+; CHECK-VL512B-NEXT:    seqz a0, a0
+; CHECK-VL512B-NEXT:    ret
+;
+; CHECK-VL1024B-LABEL: vreduce_and_v64i1:
+; CHECK-VL1024B:       # %bb.0:
+; CHECK-VL1024B-NEXT:    li a0, 64
+; CHECK-VL1024B-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-VL1024B-NEXT:    vmnot.m v8, v0
+; CHECK-VL1024B-NEXT:    vcpop.m a0, v8
+; CHECK-VL1024B-NEXT:    seqz a0, a0
+; CHECK-VL1024B-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_v128i1(<128 x i1> %v) {
+; CHECK-VL128B-LABEL: vreduce_and_v128i1:
+; CHECK-VL128B:       # %bb.0:
+; CHECK-VL128B-NEXT:    li a0, 128
+; CHECK-VL128B-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-VL128B-NEXT:    vmnot.m v8, v0
+; CHECK-VL128B-NEXT:    vcpop.m a0, v8
+; CHECK-VL128B-NEXT:    seqz a0, a0
+; CHECK-VL128B-NEXT:    ret
+;
+; CHECK-VL256B-LABEL: vreduce_and_v128i1:
+; CHECK-VL256B:       # %bb.0:
+; CHECK-VL256B-NEXT:    li a0, 128
+; CHECK-VL256B-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-VL256B-NEXT:    vmnot.m v8, v0
+; CHECK-VL256B-NEXT:    vcpop.m a0, v8
+; CHECK-VL256B-NEXT:    seqz a0, a0
+; CHECK-VL256B-NEXT:    ret
+;
+; CHECK-VL512B-LABEL: vreduce_and_v128i1:
+; CHECK-VL512B:       # %bb.0:
+; CHECK-VL512B-NEXT:    li a0, 128
+; CHECK-VL512B-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-VL512B-NEXT:    vmnot.m v8, v0
+; CHECK-VL512B-NEXT:    vcpop.m a0, v8
+; CHECK-VL512B-NEXT:    seqz a0, a0
+; CHECK-VL512B-NEXT:    ret
+;
+; CHECK-VL1024B-LABEL: vreduce_and_v128i1:
+; CHECK-VL1024B:       # %bb.0:
+; CHECK-VL1024B-NEXT:    li a0, 128
+; CHECK-VL1024B-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-VL1024B-NEXT:    vmnot.m v8, v0
+; CHECK-VL1024B-NEXT:    vcpop.m a0, v8
+; CHECK-VL1024B-NEXT:    seqz a0, a0
+; CHECK-VL1024B-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_v256i1(<256 x i1> %v) {
+; CHECK-VL128B-LABEL: vreduce_and_v256i1:
+; CHECK-VL128B:       # %bb.0:
+; CHECK-VL128B-NEXT:    li a0, 128
+; CHECK-VL128B-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-VL128B-NEXT:    vmnand.mm v8, v0, v8
+; CHECK-VL128B-NEXT:    vcpop.m a0, v8
+; CHECK-VL128B-NEXT:    seqz a0, a0
+; CHECK-VL128B-NEXT:    ret
+;
+; CHECK-VL256B-LABEL: vreduce_and_v256i1:
+; CHECK-VL256B:       # %bb.0:
+; CHECK-VL256B-NEXT:    li a0, 256
+; CHECK-VL256B-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-VL256B-NEXT:    vmnot.m v8, v0
+; CHECK-VL256B-NEXT:    vcpop.m a0, v8
+; CHECK-VL256B-NEXT:    seqz a0, a0
+; CHECK-VL256B-NEXT:    ret
+;
+; CHECK-VL512B-LABEL: vreduce_and_v256i1:
+; CHECK-VL512B:       # %bb.0:
+; CHECK-VL512B-NEXT:    li a0, 256
+; CHECK-VL512B-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-VL512B-NEXT:    vmnot.m v8, v0
+; CHECK-VL512B-NEXT:    vcpop.m a0, v8
+; CHECK-VL512B-NEXT:    seqz a0, a0
+; CHECK-VL512B-NEXT:    ret
+;
+; CHECK-VL1024B-LABEL: vreduce_and_v256i1:
+; CHECK-VL1024B:       # %bb.0:
+; CHECK-VL1024B-NEXT:    li a0, 256
+; CHECK-VL1024B-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-VL1024B-NEXT:    vmnot.m v8, v0
+; CHECK-VL1024B-NEXT:    vcpop.m a0, v8
+; CHECK-VL1024B-NEXT:    seqz a0, a0
+; CHECK-VL1024B-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v256i1(<256 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_v512i1(<512 x i1> %v) {
+; CHECK-VL128B-LABEL: vreduce_and_v512i1:
+; CHECK-VL128B:       # %bb.0:
+; CHECK-VL128B-NEXT:    li a0, 128
+; CHECK-VL128B-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-VL128B-NEXT:    vmand.mm v8, v8, v10
+; CHECK-VL128B-NEXT:    vmand.mm v9, v0, v9
+; CHECK-VL128B-NEXT:    vmnand.mm v8, v9, v8
+; CHECK-VL128B-NEXT:    vcpop.m a0, v8
+; CHECK-VL128B-NEXT:    seqz a0, a0
+; CHECK-VL128B-NEXT:    ret
+;
+; CHECK-VL256B-LABEL: vreduce_and_v512i1:
+; CHECK-VL256B:       # %bb.0:
+; CHECK-VL256B-NEXT:    li a0, 256
+; CHECK-VL256B-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-VL256B-NEXT:    vmnand.mm v8, v0, v8
+; CHECK-VL256B-NEXT:    vcpop.m a0, v8
+; CHECK-VL256B-NEXT:    seqz a0, a0
+; CHECK-VL256B-NEXT:    ret
+;
+; CHECK-VL512B-LABEL: vreduce_and_v512i1:
+; CHECK-VL512B:       # %bb.0:
+; CHECK-VL512B-NEXT:    li a0, 512
+; CHECK-VL512B-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-VL512B-NEXT:    vmnot.m v8, v0
+; CHECK-VL512B-NEXT:    vcpop.m a0, v8
+; CHECK-VL512B-NEXT:    seqz a0, a0
+; CHECK-VL512B-NEXT:    ret
+;
+; CHECK-VL1024B-LABEL: vreduce_and_v512i1:
+; CHECK-VL1024B:       # %bb.0:
+; CHECK-VL1024B-NEXT:    li a0, 512
+; CHECK-VL1024B-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-VL1024B-NEXT:    vmnot.m v8, v0
+; CHECK-VL1024B-NEXT:    vcpop.m a0, v8
+; CHECK-VL1024B-NEXT:    seqz a0, a0
+; CHECK-VL1024B-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v512i1(<512 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_v1024i1(<1024 x i1> %v) {
+; CHECK-VL128B-LABEL: vreduce_and_v1024i1:
+; CHECK-VL128B:       # %bb.0:
+; CHECK-VL128B-NEXT:    li a0, 128
+; CHECK-VL128B-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-VL128B-NEXT:    vmand.mm v10, v10, v14
+; CHECK-VL128B-NEXT:    vmand.mm v8, v8, v12
+; CHECK-VL128B-NEXT:    vmand.mm v9, v9, v13
+; CHECK-VL128B-NEXT:    vmand.mm v11, v0, v11
+; CHECK-VL128B-NEXT:    vmand.mm v8, v8, v10
+; CHECK-VL128B-NEXT:    vmand.mm v9, v11, v9
+; CHECK-VL128B-NEXT:    vmnand.mm v8, v9, v8
+; CHECK-VL128B-NEXT:    vcpop.m a0, v8
+; CHECK-VL128B-NEXT:    seqz a0, a0
+; CHECK-VL128B-NEXT:    ret
+;
+; CHECK-VL256B-LABEL: vreduce_and_v1024i1:
+; CHECK-VL256B:       # %bb.0:
+; CHECK-VL256B-NEXT:    li a0, 256
+; CHECK-VL256B-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-VL256B-NEXT:    vmand.mm v8, v8, v10
+; CHECK-VL256B-NEXT:    vmand.mm v9, v0, v9
+; CHECK-VL256B-NEXT:    vmnand.mm v8, v9, v8
+; CHECK-VL256B-NEXT:    vcpop.m a0, v8
+; CHECK-VL256B-NEXT:    seqz a0, a0
+; CHECK-VL256B-NEXT:    ret
+;
+; CHECK-VL512B-LABEL: vreduce_and_v1024i1:
+; CHECK-VL512B:       # %bb.0:
+; CHECK-VL512B-NEXT:    li a0, 512
+; CHECK-VL512B-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-VL512B-NEXT:    vmnand.mm v8, v0, v8
+; CHECK-VL512B-NEXT:    vcpop.m a0, v8
+; CHECK-VL512B-NEXT:    seqz a0, a0
+; CHECK-VL512B-NEXT:    ret
+;
+; CHECK-VL1024B-LABEL: vreduce_and_v1024i1:
+; CHECK-VL1024B:       # %bb.0:
+; CHECK-VL1024B-NEXT:    li a0, 1024
+; CHECK-VL1024B-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-VL1024B-NEXT:    vmnot.m v8, v0
+; CHECK-VL1024B-NEXT:    vcpop.m a0, v8
+; CHECK-VL1024B-NEXT:    seqz a0, a0
+; CHECK-VL1024B-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.v1024i1(<1024 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_nxv1i1(<vscale x 1 x i1> %v) {
+; CHECK-LABEL: vreduce_and_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.nxv1i1(<vscale x 1 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_nxv2i1(<vscale x 2 x i1> %v) {
+; CHECK-LABEL: vreduce_and_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_nxv4i1(<vscale x 4 x i1> %v) {
+; CHECK-LABEL: vreduce_and_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.nxv4i1(<vscale x 4 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_nxv8i1(<vscale x 8 x i1> %v) {
+; CHECK-LABEL: vreduce_and_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.nxv8i1(<vscale x 8 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_nxv16i1(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: vreduce_and_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_nxv32i1(<vscale x 32 x i1> %v) {
+; CHECK-LABEL: vreduce_and_nxv32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_nxv64i1(<vscale x 64 x i1> %v) {
+; CHECK-LABEL: vreduce_and_nxv64i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT:    vmnot.m v8, v0
+; CHECK-NEXT:    vcpop.m a0, v8
+; CHECK-NEXT:    seqz a0, a0
+; CHECK-NEXT:    ret
+  %red = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %v)
+  ret i1 %red
+}
+
+define zeroext i1 @vreduce_and_nxv128i1(<vscale x 128 x i1> %v) {
+; CHECK-LABEL: vreduce_and_nxv128i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
+; CHECK-NEXT:    vmand.mm v8, v0, v8
+; CHECK-NEXT:    vmnot.m v8, v8
----------------
topperc wrote:

The optimization for scalable vectors should be present after #121812

https://github.com/llvm/llvm-project/pull/119160


More information about the llvm-commits mailing list