[llvm] [X86] Combine `uitofp <v x i32> to <v x half>` (PR #121809)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 6 13:50:51 PST 2025
https://github.com/abhishek-kaushik22 updated https://github.com/llvm/llvm-project/pull/121809
>From 9f62f4105035091b57c6912a22f3e0d7f72bdf2b Mon Sep 17 00:00:00 2001
From: abhishek-kaushik22 <abhishek.kaushik at intel.com>
Date: Tue, 7 Jan 2025 03:19:13 +0530
Subject: [PATCH] Update LegalizeVectorOps.cpp
---
.../SelectionDAG/LegalizeVectorOps.cpp | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 154c8aea6bcd17..2be9239202b021 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -1776,6 +1776,27 @@ void VectorLegalizer::ExpandUINT_TO_FLOAT(SDNode *Node,
assert((BW == 64 || BW == 32) &&
"Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
+ // If STRICT_/FMUL is not supported by the target (in case of f16) replace the
+ // UINT_TO_FP with a larger float and round to the smaller type
+ if ((!IsStrict && TLI.getOperationAction(ISD::FMUL, Node->getValueType(0)) ==
+ TargetLowering::Expand) ||
+ (IsStrict &&
+ TLI.getOperationAction(ISD::STRICT_FMUL, Node->getValueType(0)) ==
+ TargetLowering::Expand)) {
+ EVT FPVT = BW == 32 ? MVT::f32 : MVT::f64;
+ SDLoc DL(Node);
+ unsigned Round = IsStrict ? ISD::STRICT_FP_ROUND : ISD::FP_ROUND;
+ unsigned UIToFP = IsStrict ? ISD::STRICT_UINT_TO_FP : ISD::UINT_TO_FP;
+ SDValue Result = DAG.getNode(
+ Round, DL, Node->getValueType(0),
+ DAG.getNode(UIToFP, DL, VT.changeVectorElementType(FPVT), Src),
+ DAG.getTargetConstant(
+ 0, DL,
+ DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout())));
+ Results.push_back(Result);
+ return;
+ }
+
SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT);
// Constants to clear the upper part of the word.
More information about the llvm-commits
mailing list