[llvm] [RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (PR #121705)

[Michael Maitland via llvm-commits]

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@@ -732,6 +747,30 @@ static bool isSupportedInstr(const MachineInstr &MI) {
     return false;
 
   switch (RVV->BaseInstr) {
+  // Vector Unit-Stride Instructions
+  // Vector Strided Instructions
+  case RISCV::VLE8_V:
+  case RISCV::VLM_V:
+  case RISCV::VLSE8_V:
+  case RISCV::VLE8FF_V:
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michaelmaitland wrote:

> These instructions execute as a regular load except that they will only take a trap caused by a synchronous exception on element 0. If element 0 raises an exception, vl is not modified, and the trap is taken. If an element > 0 raises an exception, the corresponding trap is not taken, and the vector length vl is reduced to the index of the element that would have raised an exception.

My thought was that it should not affect the result. Is this an incorrect understanding?

https://github.com/llvm/llvm-project/pull/121705