[llvm] [RISCV] GISel custom lowering for G_ADD/G_SUB (PR #121587)

[Luke Quinn via llvm-commits]

================
@@ -1330,6 +1338,25 @@ bool RISCVLegalizerInfo::legalizeCustom(
       return true;
     return Helper.lowerConstant(MI);
   }
+  case TargetOpcode::G_SUB:
+  case TargetOpcode::G_ADD: {
+    Helper.Observer.changingInstr(MI);
+    Helper.widenScalarSrc(MI, LLT::scalar(64), 1, TargetOpcode::G_ANYEXT);
+    Helper.widenScalarSrc(MI, LLT::scalar(64), 2, TargetOpcode::G_ANYEXT);
+
+    Register DstALU = MRI.createGenericVirtualRegister(sXLen);
+    Register DstSext = MRI.createGenericVirtualRegister(sXLen);
----------------
lquinn2015 wrote:

>From a being new perspective its is a little hard to understand from the headers what DstOp is coercionable but i do like being able to just i give a LLT for the buildSExtInReg. I tried to do the same for the SrcOp naively but that didn't seem to work the same. Maybe its possible but I am not reading the correct header for it!

https://github.com/llvm/llvm-project/pull/121587