[llvm] select v_sat_pk from two i16 or v2i16 (PR #121124)

[Pierre van Houtryve via llvm-commits]

================
@@ -315,6 +315,55 @@ def srl_16 : PatFrag<
   (ops node:$src0), (srl_oneuse node:$src0, (i32 16))
 >;
 
+def clamp_s16_u8 : PatFrag<
+  (ops node:$src),
+  (i16 (AMDGPUsmed3 $src, (i16 0), (i16 255)))
+>;
+
+def conc_lo_u8_i16 : PatFrags<
+  (ops node:$src0, node:$src1),
+  [
+    (or
+      (i16 $src0),
+      (shl (i16 $src1), (i16 8))
+    ),
+    (or
+      (and (i16 $src0), (i16 255)),
+      (shl (i16 $src1), (i16 8))
+    )
+  ]
+>;
+
+def clamp_v2i16_u8 : PatFrags<
+  (ops node:$src),
+  [
+    (v2i16 (smax (smin $src, (build_vector (i16 255), (i16 255))), (build_vector (i16 0), (i16 0)))),
+    (v2i16 (smin (smax $src, (build_vector (i16 0), (i16 0))), (build_vector (i16 255), (i16 255))))
+  ]
+>;
+
+def conc_lo_v2i16_i16 : PatFrags<
----------------
Pierre-vh wrote:

@arsenm Isn't matching bitwise ops fragile?

Wouldn't it be better to make v2i8 legal, address codegen regressions (maybe by handling it in TargetLowering/CC stuff as well), then come back to this?

I'm afraid the patterns would constantly break whenever a new combine is added for the bitwise ops like shift/and/or/etc. if we try to match v2i8 ops that are lowered as bitwise ops

https://github.com/llvm/llvm-project/pull/121124