[llvm] [RISCV]Update CSRs (PR #121634)

[Craig Topper via llvm-commits]

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@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
 def : SysReg<"hvip", 0x645>;
 def : SysReg<"htinst", 0x64A>;
 def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
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topperc wrote:

Need `let isRV32Only = 1 in`

Should this be in the same group as "hedeleg"

https://github.com/llvm/llvm-project/pull/121634