[llvm] [RISCV]Update CSRs (PR #121634)

[Craig Topper via llvm-commits]

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@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
 def : SysReg<"mip", 0x344>;
 def : SysReg<"mtinst", 0x34A>;
 def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
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topperc wrote:

Need `let isRV32Only = 1 in`

Should this be in the same group with "medeleg"?

https://github.com/llvm/llvm-project/pull/121634